Ph.D. Intern - AI/ML & Design Automation

Job Title

Ph.D. Intern - AI/ML & Design Automation

Role Summary

Doctoral-level internship placing candidates on teams that apply machine learning to chip design (EDA automation, design-space exploration, predictive modeling) or build internal enterprise AI tools (LLM integrations, agentic workflows, RAG pipelines).

Work is applied research: deploy models and tools on production design data and engineering workflows to reduce design cycles and improve silicon outcomes.

Experience Level

Entry-level (internship).

Responsibilities

Day-to-day responsibilities vary by track; typical activities include:

• Research, develop, and apply ML models (GNNs, reinforcement learning, generative approaches) to chip-design problems such as placement, routing, timing closure, and power estimation.
• Use production EDA flows and real design data from advanced nodes to train and validate models.
• Build predictive models to reduce design iterations and improve first-pass silicon success.
• Design, implement, and evaluate LLM-based tools, agentic workflows, and RAG pipelines for engineering teams.
• Fine-tune models, implement prompt engineering frameworks, and measure model performance, safety, and reliability in production environments.
• Collaborate with analog, digital, physical design, IT, security, and platform teams to integrate solutions.
• Present research and implementation results to engineering leadership and contribute to technical documentation.

Requirements

Must-have skills and applied experience; track-specific items follow:

• Hands-on experience building, evaluating, and deploying ML systems in production using frameworks such as PyTorch or TensorFlow.
• Production-quality Python development; familiarity with version control (Git) and software development best practices.
• Rigorous experimental methodology: design experiments, measure results, and draw defensible conclusions from data.
• Clear technical communication for both research and engineering audiences.
• Track 1 (Hardware): coursework or research experience in VLSI, digital/analog circuit design, computer architecture, or EDA; familiarity with graph-based ML methods (GNNs), reinforcement learning, or generative models applied to structured engineering data; exposure to EDA tools (Cadence, Synopsys, or equivalent) is a strong plus.
• Track 2 (Enterprise AI): experience designing and implementing agentic GenAI systems and RAG pipelines; hands-on knowledge of transformer-based and multimodal architectures; familiarity with orchestration tools and frameworks such as LangChain, LlamaIndex, Hugging Face, or similar; ability to benchmark and iterate on model performance.
• Preferred: experience with multi-agent orchestration frameworks, end-to-end data pipeline development, and independently translating current AI literature into working systems.

Education Requirements

Candidates should be currently enrolled in a Ph.D. program (Ph.D. student) in Computer Science, Electrical Engineering, Data Science, or a related field with a research focus in machine learning, AI systems, or a closely related area.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.