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ASIC Design Engineer - Clocks IP

NVIDIA
September 11, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$116,000 - $218,500 USD yearly
RTL Design Jobs, Level - Entry or Early Career

Job Title

ASIC Design Engineer - Clocks IP

Role Summary

Join the clocks team responsible for architecting and delivering GPU and CPU clocking solutions across micro-architecture, RTL, physical implementation, and silicon bring-up. The team partners with front-end architects, physical design, timing, verification, DFT and software teams to define clocking topology, sequencing, and to triage silicon issues.

Work focuses on improving power, performance and area (PPA) and enabling high-speed, scalable on-chip clocking for advanced ASICs.

Experience Level

Entry-level - expects around 2+ years of relevant ASIC/RTL experience.

Responsibilities

Primary responsibilities include:

  • Architect clock domains to meet functional, physical and test requirements.
  • Design GPU/CPU clocking logic and topologies in RTL, balancing architectural, physical and timing constraints.
  • Collaborate with physical design and timing teams to address clocking challenges and ensure timing closure.
  • Evaluate PPA trade-offs across DFx, physical implementation and synthesis to improve chip performance and area.
  • Deliver clock RTL and documentation to verification, timing, and DFT teams.
  • Participate in ASIC execution lifecycle from micro-architecture through sign-off and silicon bring-up; assist in silicon and programming bug triage.

Requirements

Core technical skills and experience required, plus preferred strengths:

  • Must-have: Deep understanding of logic optimization techniques and PPA trade-offs.
  • Must-have: RTL design with Verilog, verification and logic synthesis experience.
  • Must-have: Strong scripting/coding skills (Python or equivalent).
  • Must-have: Strong interpersonal skills and ability to collaborate across multiple teams.
  • Preferred: Experience with clock controllers and clocks logic design.
  • Preferred: Familiarity with physical silicon issues (noise, crosstalk, OCV) and scalable design/architecture.
  • Nice-to-have: Hands-on silicon debug and experience implementing on-chip clocking networks.

Education Requirements

BS in Electrical Engineering or equivalent practical experience required; MS preferred.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-09-11