Ph.D. Intern - Advanced Packaging & Physical Integration

Job Title

Ph.D. Intern - Advanced Packaging & Physical Integration

Role Summary

Support Marvell's advanced packaging team on production-focused packaging design and analysis for AI accelerators and high-speed connectivity platforms. Work spans electrical, thermal, and mechanical modeling of multi-die packages, interposers, and chiplet integration schemes.

Projects are integrated with chip design, assembly, and test teams and target production platforms used by hyperscalers.

Experience Level

Entry-level internship for doctoral candidates (Ph.D. students). No specific years of industry experience required; expect relevant research experience.

Responsibilities

Typical responsibilities for this internship include:

• Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces (including 224G SerDes, die-to-die links, and HBM interfaces).
• Develop and execute thermal and mechanical simulation models for 2.5D and 3D chiplet packages to evaluate heat dissipation, warpage, and reliability.
• Contribute to physical design and layout of package substrates, RDL interposers, and chiplet integration schemes.
• Collaborate with chip design, assembly, and test engineering to validate packaging assumptions against silicon measurements and production data.
• Use industry-standard EDA and simulation tools (Ansys, Cadence Sigrity, or equivalents) to model and optimize package-level performance.
• Present analysis results and design recommendations in engineering reviews.

Requirements

Must-have technical skills and experience:

• Hands-on research or project experience in semiconductor packaging, signal integrity, power integrity, thermal-mechanical simulation, or heterogeneous integration.
• Experience with package-level SI/PI analysis, thermal-mechanical modeling, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization.
• Strong fundamentals in electromagnetics, heat transfer, or materials mechanics sufficient to build and interpret simulation models.
• Proficiency with relevant simulation tools (Ansys HFSS/Icepak, Cadence Sigrity, or equivalents) and ability to work independently.
• Clear technical communication skills; ability to present and defend recommendations to engineering teams.

Nice-to-have:

• Experience with high-speed serial SI at 100G/lane or higher (eye diagrams, impedance matching, crosstalk).
• Familiarity with advanced packaging technologies (CoWoS, FOPLP, RDL interposers, flip-chip BGA) and PDN design for high-current applications.
• Exposure to co-packaged optics, photonic-electronic co-design, and DFM/reliability for multi-die packages.

Reasonable accommodation contact: TAOps@marvell.com.

Education Requirements

Currently enrolled in a Ph.D. program (doctoral candidate) in Electrical Engineering, Materials Science, Mechanical Engineering, Physics, or a closely related technical field. Ph.D. enrollment is required; equivalent-experience language is not provided.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.