Job Title
Performance Architecture Engineer
Role Summary
Responsible for microarchitecture performance analysis and modeling for high-performance CPU and AI designs. Work with hardware and performance-model teams to identify performance bottlenecks, validate and extend performance models, and recommend optimizations to workloads or microarchitecture.
Experience Level
Mid-level. Years of experience not specified.
Responsibilities
Key responsibilities include:
- Analyze CPU microarchitecture performance and identify bottlenecks.
- Compare hardware behavior to performance models and investigate discrepancies.
- Develop and extend performance models; implement and validate microarchitecture ideas in models.
- Design, run, and analyze benchmarks and microbenchmarks to characterize performance.
- Analyze workload characteristics and recommend optimizations for workloads or microarchitecture.
- Present findings and recommendations to engineering teams.
Requirements
Core skills and experience:
- Practical experience in computer architecture and processor microarchitecture.
- Experience in microarchitecture performance analysis.
- Experience with benchmarking and microbenchmark design.
- Assembly and C/C++ programming experience.
- Waveform analysis experience.
- Familiarity with Git or other source control and Linux-based development; Python/shell scripting.
- Good presentation and communication skills.
Nice-to-have:
- Experience with the RISC-V V-extension.
- Experience in performance-model development.
Education Requirements
Not specified.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.

Date Posted: 2026-08-04