PE Logic Design
RambusJob Title
Principal Logic Design Engineer (PE Logic Design)
Role Summary
Individual contributor on the Silicon IP (SIP) team responsible for micro-architecture and RTL design of high-performance memory controller blocks for data center and AI applications. The role partners with verification, physical design, and customer-facing teams to drive PPA, functionality, and delivery.
Team location: Hillsboro, OR. Hybrid work model with an expected on-site average of three days per week.
Experience Level
Level: Senior. The posting requests experienced engineers (guidance provided in Education Requirements below).
Responsibilities
Primary responsibilities include design, analysis, and cross-team collaboration:
- Define micro-architecture and implement RTL for critical blocks (schedulers, command pipelines, coherency/ordering logic, system interfaces).
- Analyze performance, power, and area (PPA) trade-offs and recommend design choices based on quantitative data.
- Collaborate with verification to shape test plans, improve coverage, and debug regression failures; provide RTL fixes when required.
- Work with physical design to resolve timing, power, and congestion issues.
- Support pre-sales (FAE) and post-sales (AE) technical engagements with customers.
Requirements
Core technical skills and experience required; additional desirable skills listed separately.
- Strong SystemVerilog/Verilog RTL design expertise.
- Experience with Questa, Incisive, or VCS simulators and RTL-driven debug.
- Proficiency in scripting (Python, Perl, TCL) for automation and verification support.
- Proven ability to debug regression failures and implement RTL fixes.
- Solid verbal and written communication skills and demonstrated project management in multi-team environments.
- Experience with ASIC or FPGA logic design and collaboration with verification and physical design teams.
Nice-to-have:
- ASIC synthesis, timing constraints, CDC/RDC experience.
- UVM verification experience.
- Memory subsystem expertise (HBM, LPDDR) and AMBA AXI or CHI protocol experience.
Education Requirements
Posting specifies a technical degree: BSEE with 10+ years of logic design experience, or MSEE with 8+ years of logic design experience. Degrees noted: BSEE, MSEE (Electrical Engineering). No other certifications or explicit "equivalent experience" language was provided.
About the Company
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
