PD IREM Lead (PHY‑V Lead)

Job Title

PD IREM Lead (PHY‑V Lead)

Role Summary

Lead physical verification sign-off, full-chip integration, and packaging interface planning for advanced SoC programs. Own DRC/LVS closure, GDS assembly, and RDL/IO-escape strategy while coordinating cross-functional teams (PD, PnR, Analog, Packaging, foundry).

Experience Level

Senior — typically requires 10–15+ years of experience in Physical Design, Physical Verification, or SoC integration.

Responsibilities

Primary responsibilities include physical verification sign-off, top-level integration, packaging interface planning, and tapeout execution.

• Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level and deliver sign-off-clean GDS for tapeout.
• Define and enforce sign-off methodology, foundry rule decks, waivers, and risk assessments.
• Lead top-level integration: GDS assembly, hierarchical LVS reconciliation, and resolution of boundary/connectivity issues.
• Plan RDL, bump mapping, IO escape routing, and die–package interface in collaboration with packaging and SI/PI teams.
• Own tapeout readiness: sign-off checklists, closure tracking, tapeout reviews, and milestone reporting.
• Develop and optimize physical verification flows (Calibre/ICV/Pegasus); drive automation and runtime/debug efficiency.
• Lead debug and root-cause resolution for complex DRC violations and LVS mismatches; minimize waivers.
• Mentor PHY‑V engineers and act as primary escalation point for sign-off issues across teams and foundry.

Requirements

Key technical and leadership requirements. Education details are listed separately under Education Requirements.

• Must-have: 10–15+ years in Physical Design / Physical Verification / SoC Integration with proven ownership of sign-off closure for complex SoCs.
• Must-have: Deep expertise in DRC, LVS, ERC, antenna checks and full PD flow (RTL → GDS → sign-off).
• Must-have: Hands-on experience with Calibre, ICV, Pegasus or equivalent physical verification tools.
• Must-have: Experience with advanced process nodes (7nm and below) and tapeout execution under schedule pressure.
• Must-have: Strong leadership and cross-functional coordination skills; experience mentoring engineers and driving closure across PD, PnR, Analog, Packaging, and foundry.
• Nice-to-have: RDL planning, bump mapping, and advanced packaging (flip-chip / 2.5D / 3D) experience.
• Nice-to-have: Exposure to IR/EM, SI/PI, PEX, reliability checks and chiplet/3D-IC methodologies.
• Nice-to-have: Strong scripting skills (TCL/Python) for automation and flow optimization.

Education Requirements

B.Tech or M.Tech in Electronics or Electrical Engineering specified.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.