PD Engineer

Job Title

PD Engineer

Role Summary

Member of the Hardware Engineering team responsible for physical design and timing signoff for high-speed cores. The role leads block- and chip-level physical implementation activities from RTL to GDSII, optimizes PPA (performance, power, area) and PDN, and collaborates with STA, verification, and cross-functional groups to deliver silicon-ready designs.

Experience Level

Senior-level. The posting includes varied experience ranges but expects experienced candidates with substantial IC physical-design and timing-signoff experience; the listing also includes minimums for advanced degrees with fewer years of experience.

Responsibilities

The position focuses on physical implementation, timing closure, and power/PDN convergence across block and chip scopes.

• Lead physical design and timing signoff for high-speed cores and complex blocks.
• Drive RTL-to-GDSII implementation, including layout convergence and signoff flows.
• Execute STA and PDN analysis and remediation to meet PPA targets.
• Define and apply low-power techniques (power gating, multi-Vt, supply management) in implementation flows.
• Diagnose deep sub-micron issues (leakage, signal integrity, DFM) and mitigate critical timing paths.
• Automate tasks and flows using scripting (Tcl/Perl) and develop tool-based solutions.
• Collaborate with verification, RTL, packaging and test teams to resolve constraints and integration issues.
• Lead technical deliveries and mentor or coordinate a small team of engineers.

Requirements

Required technical skills and experience for successful performance in this role.

• Experience in physical design and timing signoff for high-speed cores (demonstrable block- or chip-level work).
• Practical experience with high-frequency design convergence to meet PPA targets and PDN methodology.
• Hands-on experience with STA and PDN activities at block and chip level.
• Proven ability to deliver RTL-to-GDSII implementation and resolve constraints/verification issues.
• Knowledge of low-power implementation techniques (power gating, multi-Vt flows, power-supply management).
• Circuit-level understanding of timing-critical paths and deep sub-micron effects (leakage, SI, DFM).
• Proficiency in scripting for automation (Tcl, Perl) and strong problem-solving skills.
• Ability to work independently and coordinate small engineering teams to meet technical milestones.
• Nice-to-have: prior experience with yield bring-up, packaging/test interactions, or leadership of multi-disciplinary delivery efforts.

Education Requirements

Qualifications listed include: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field (typically paired with 2+ years of hardware/physical-design experience); OR Master's degree in these fields (typically paired with 1+ year experience); OR PhD in a related field. The posting also references candidates with Bachelor’s/Master’s degrees and 7+ years of IC design experience for senior roles.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.