Padring Verification Engineer

Job Title

Padring Verification Engineer

Role Summary

Join NVIDIA's System-on-Chip (SoC) group to develop scalable padring verification methodologies, tools, and automation, and to execute padring verification and connectivity signoff for GPU and Tegra projects. You will work across RTL, DFT, Physical Design, CAD, Package Design, and Software teams to identify and resolve padring integration issues and improve verification quality.

This role focuses on padring RTL integration, connectivity verification, DFT-related padring logic, and verification signoff for complex SoCs.

Experience Level

Mid-level; typically 1–8 years of relevant ASIC/SoC, RTL verification, or integration experience.

Responsibilities

Key responsibilities include developing methodologies and executing padring verification through signoff:

• Develop and maintain scalable padring verification methodologies, infrastructure, and automation for RTL integration, connectivity verification, and chip assembly.
• Execute padring verification and connectivity signoff for GPU and Tegra projects; analyze results, debug failures, and drive issues to closure.
• Verify DFT-related padring logic, including boundary scan, test-access connectivity, control/configuration logic, and integration correctness.
• Define verification plans and develop assertions, checkers, testbenches, coverage goals, and regression suites for padring functionality and SoC integration.
• Build tools and flows to detect padring integration issues early and improve debug efficiency and signoff quality.
• Collaborate with DFT, RTL, Physical Design, CAD, Package Design, and Software teams to resolve complex cross-domain issues and meet project milestones.
• Apply AI-assisted approaches where useful to improve methodology automation and debugging.

Requirements

Must-have skills and experience for successful candidates:

• 1–8 years of experience in ASIC/SoC design, RTL verification, SoC integration, or methodology development.
• Strong understanding of RTL and SoC verification concepts: simulation, formal checks, assertions, coverage, regressions, debug, and signoff.
• Familiarity with DFT concepts, particularly boundary scan, JTAG/test-access mechanisms, scan/test modes, and padring DFT integration.
• Experience creating verification environments, checkers, testbenches, and automation for subsystem- or SoC-level designs.
• Proficiency in Python, Perl, or similar scripting languages for testbench automation and tooling.
• Excellent analytical, problem-solving, communication, and cross-functional collaboration skills.

Nice-to-have:

• Experience or interest in AI-assisted verification tooling and automation.
• Prior exposure to padring connectivity signoff, chip assembly flows, or close work with Physical Design and Package teams.

Education Requirements

MS in Computer Engineering, Electrical Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.