Package Layout Engineer

Job Title

Package Layout Engineer

Role Summary

Design and deliver IC package substrate layouts for advanced packaging technologies, supporting signal integrity, power integrity, thermal, and manufacturing constraints. Work on multi-disciplinary packages that integrate digital, analog, and photonics components and coordinate with suppliers and assembly partners.

Experience Level

Mid-level (typical experience: 3–7 years). Candidates with the stated experience in IC package layout design are preferred.

Responsibilities

Deliver and validate substrate layouts across the product lifecycle and collaborate with cross-functional teams and external suppliers.

• Produce IC package substrate layouts for standard and advanced packaging (2.5D/3D, interposers, fan-out, etc.).
• Provide preliminary substrate designs and floorplanning during concept and architecture phases.
• Apply layout design rules, stack-up, and implementation guidelines with substrate suppliers and OSATs.
• Generate fab files and coordinate DFM/DFA closure with manufacturing partners.
• Design layouts meeting signal integrity, power integrity, thermal, and mechanical requirements and support iterative SI/PI refinement.
• Coordinate tape-outs and schedule-driven deliverables across functional teams.
• Support and improve design automation and verification workflows (scripting, tool integration).

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 3–5+ years of IC package layout design experience, including floorplanning and escape routing.
• Proficient with Allegro X APD (layout implementation and routing).
• Understanding of IC package substrates, organic materials, and how materials impact layout and signal/power behavior.
• Experience with bump patterns (micro-bumps / hybrid bonding) and die-to-die interface topologies.
• Ability to collaborate with suppliers and OSATs to implement manufacturing requirements (DFM/DFA).
• Effective communication and cross-functional collaboration skills.
• Ability to comply with U.S. export control requirements.
• Nice-to-have: familiarity with Cadence Integrity 3DIC, Expedition Package Designer, Pads Layout, Altium.
• Nice-to-have: experience scripting for layout automation (SKILL, Python) and performing physical feasibility studies for multi-chiplet architectures.

Education Requirements

B.S. or M.S. in Electrical Engineering or a related discipline. Educational background in IC packaging or substrate layout design is preferred. The posting pairs degree expectations with several years of relevant experience (minimums referenced above).

About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.