Package Layout Design Senior Staff Engineer

Job Title

Package Layout Design Senior Staff Engineer

Role Summary

Senior engineer in Marvell's central advanced packaging organization responsible for developing high-speed microelectronic package layouts from concept through tapeout. Works with package architects, technical leads, and cross-functional teams to ensure manufacturability, electrical performance, reliability, and cost targets.

Focus areas include C4/BGA ball maps, die placement, padstacks, net assignments, PRDs, and package-level connectivity for complex 2D/2.5D packaging architectures.

Experience Level

Senior-level. The posting does not list explicit years of experience, but the role expects substantial experience in package layout and high-pin-count designs.

Responsibilities

Core responsibilities include leading package layout activities and ensuring package readiness for tapeout.

• Develop C4 and BGA ball maps optimized for SI/PI and layout efficiency.
• Plan and validate netlist mappings across dies, interposers, and substrates.
• Define die placement, padstacks, net assignments, and package-level connectivity.
• Create and maintain Package Requirement Documents (PRDs) with die arrangements and stackups.
• Ensure manufacturability and compliance with foundry and substrate manufacturing constraints.
• Collaborate with chip, board, and electrical simulation teams for package-system co-design and optimization.
• Contribute to tool, process, and flow development; maintain libraries and automation scripts.
• Support validation of thermal and mechanical constraints and work across global teams.

Requirements

Must-have skills and experience:

• Proven experience with package layout including RDL and substrate routing and tapeout for large, complex packages.
• Experience developing C4 and BGA ball maps for high-pin-count designs.
• Proficiency with Cadence OrbitIO, Integrity System Planner (ISP), or equivalent tools.
• Strong understanding of package design rules, breakout, place-and-route, signal shielding, reference planes, and power distribution.
• Solid grasp of SI/PI fundamentals at substrate, board, and system levels.
• Familiarity with foundry design rules and substrate manufacturing constraints.
• Experience with scripting/automation and contributing to tool/process development.
• Strong communication, presentation, and documentation skills and experience working across cross-functional and global teams.

Nice-to-have:

• Familiarity with signal and power simulation tools and interpreting results.
• Knowledge of 2D, 2.5D, and advanced packaging architectures (CoWoS, EMIB, CPO, CPC).
• High-level understanding of thermal and mechanical constraints such as warpage and TIM.

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.