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Package Engineer

Delos Data
August 31, 2026
Full-time
On-site
Palo Alto, California, United States
$180,000 - $240,000 USD yearly
Other Semiconductor Jobs, Level - Senior

Job Title

Package Engineer

Role Summary

Senior packaging engineer responsible for architecting and delivering advanced multi-die IC packages for high-performance AI accelerators. The role partners with IC design, physical design, SI/PI, board teams, and external foundries/OSATs to meet electrical, thermal, mechanical, and manufacturability targets.

Experience Level

Senior-level. Specific years of experience not stated.

Responsibilities

Design and deliver package solutions that meet system-level performance, thermal, and manufacturability requirements.

  • Select and define multi-die package types (MCM, 2.5D, 3D, fan-out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
  • Define package specifications including bump/ball maps, interposer requirements, mechanical constraints, substrate stack-ups, bump/ball pitch, routing and via structures.
  • Perform high-speed signal escaping, routing, and power distribution network design and verification.
  • Manage subcontractors and engage directly with TSMC and OSAT partners on bumping, substrate options, and advanced packaging flows.
  • Partner with IC design, physical design, SI/PI, and board teams to align package requirements with system needs.
  • Support package-level bring-up, failure analysis, debug, and qualification.
  • Evaluate emerging packaging technologies and drive adoption for next-generation products.

Requirements

Must-have technical skills and experience to perform the role; nice-to-have items noted.

  • Experience with multi-die package design and UCIe (AP/SP) integration.
  • Understanding of substrate materials, stack-ups, mechanical constraints, and manufacturability considerations.
  • Familiarity with SI/PI concepts to collaborate effectively with electrical teams.
  • Experience managing packaging subcontractors and coordinating with foundries/OSATs.
  • Experience interfacing with TSMC or similar foundries on bumping and packaging options.
  • Experience in high-speed signal escaping, routing, and PDN design.
  • Nice-to-have: familiarity with package modeling tools (HFSS, Sigrity, or similar).

Education Requirements

B.S. or M.S. in Electrical Engineering or a related field.


About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.

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Date Posted: 2026-08-29