Package Design Staff to Senior Staff Engineer

Job Title

Package Design Staff to Senior Staff Engineer

Role Summary

Senior engineer in Marvell’s central advanced packaging organization responsible for developing high‑speed IC packages from concept through tapeout. The role focuses on package architecture, signal and power integrity considerations, manufacturability, and cross‑functional collaboration with chip, board, and manufacturing teams.

Experience Level

Senior level (Staff to Senior Staff). Years of experience not specified in the posting.

Responsibilities

Primary duties include detailed package design, verification, and documentation to meet performance, reliability, and manufacturability goals.

• Drive microelectronic package development from concept through tapeout.
• Develop C4 and BGA ball maps optimized for SI/PI and layout efficiency for high‑pin‑count designs.
• Plan and validate netlist mappings across dies, interposers, and substrates; define die placement, padstacks, net assignments, and package‑level connectivity.
• Create and maintain Package Requirement Documents (PRDs) with die arrangements, stackups, and design constraints.
• Collaborate with chip, board, and electrical simulation teams to optimize package/system co‑design.
• Contribute to tool, process, and flow development; maintain libraries and develop basic automation scripts.
• Work with cross‑functional and global teams, and coordinate with foundries and substrate manufacturers to ensure manufacturability.

Requirements

Key technical skills and work requirements. Items are condensed from the posting and prioritized as must‑have vs nice‑to‑have where applicable.

• Must-have: Experience developing netlists and schematics for large, complex packages.
• Must-have: Experience creating C4 and BGA ball maps for high‑pin‑count designs.
• Must-have: Proficiency with Cadence OrbitIO / Integrity System Planner (ISP) or equivalent package design tools.
• Must-have: Strong understanding of package design rules, breakout, place and route, reference planes, power distribution, and pinout optimization.
• Must-have: Solid grasp of signal and power integrity fundamentals at substrate, board, and system levels.
• Must-have: Familiarity with foundry design rules and substrate manufacturing constraints; ability to ensure manufacturability.
• Must-have: Ability to work across global, cross‑functional teams; strong communication and documentation skills.
• Must-have: Eligibility to access export‑controlled technology; candidates may be subject to export license review.
• Nice-to-have: Experience with 2D/2.5D and advanced packaging architectures (CoWoS‑S/R/L, EMIB, CPO, CPC) and with running/interpreting SI/PI simulations.
• Nice-to-have: Understanding of thermal and mechanical package constraints (e.g., warpage, TIM).

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.