Package Design Principal Engineer

Job Title

Package Design Principal Engineer

Role Summary

Senior engineer responsible for high-speed IC package development from concept through tapeout within Marvell's central advanced packaging organization. The role focuses on package architecture, electrical performance (SI/PI), manufacturability, and creation of Package Requirement Documents (PRDs).

Works with package architects, chip and board teams, and manufacturing partners to meet performance, reliability, and cost targets. Eligible to participate in Marvell's bonus and equity plans.

Experience Level

Senior-level. 13–16 years of related professional experience.

Responsibilities

Primary responsibilities include technical ownership of package design and cross-functional coordination.

• Drive package development from concept through tapeout, selecting technologies and ensuring manufacturability, performance, reliability, and cost compliance.
• Develop C4 and BGA ball maps optimized for SI/PI and layout efficiency for high-pin-count designs.
• Plan and validate netlist mappings across dies, interposers, and substrates; define die placement, padstacks, net assignments, and package-level connectivity.
• Create and maintain Package Requirement Documents (PRDs) detailing die arrangements, stackups, and design constraints.
• Collaborate with chip, board, and electrical simulation teams for package-system co-design and optimization.
• Contribute to tool, process, and flow development; maintain libraries and develop basic automation/scripting.

Requirements

Core skills and background required or preferred for success in the role.

• 13–16 years of relevant professional experience.
• Experience developing netlists and schematics for large, complex packages.
• Experience creating C4 and BGA ball maps for high-pin-count designs.
• Proficiency with Cadence OrbitIO / Integrity System Planner (ISP) or equivalent tools.
• Strong knowledge of package design: design rules, breakout, place-and-route, signal shielding, reference planes, power distribution, and pinout optimization.
• Solid grasp of SI/PI fundamentals; familiarity with running and interpreting signal and power simulations is a plus.
• Familiarity with 2D, 2.5D and advanced packaging architectures (CoWoS, EMIB, CPO, CPC) and substrate/foundry manufacturing constraints.
• Understanding of thermal and mechanical package constraints (e.g., warpage, TIM).
• Proven ability to work across cross-functional and global teams; strong communication, presentation, and documentation skills.

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.