Package Design Engineer – Principal Engineer

Job Title

Package Design Engineer – Principal Engineer

Role Summary

Lead and develop Qualcomm's datacenter package design team to define and deliver advanced multi-die package architectures (2.5D/3D, HBM, interposers, bridges, high-density substrates) from concept through production. This senior technical leader owns package strategy, cross-functional execution, supplier engagement, and team development for high-performance compute products.

Experience Level

Senior. See Education Requirements for formal years-of-experience guidance; the role targets experienced leaders with substantial track records in advanced package engineering (preferred 15+ years for senior leadership; minimums specified under Education Requirements).

Responsibilities

Key responsibilities include technical leadership, architecture ownership, and cross-functional execution for advanced package solutions:

• Provide technical and organizational leadership: recruit, mentor, and grow a high-performing package architecture and physical-design team.
• Own end-to-end package architecture and design strategy from feasibility through qualification, ramp, and sustainment.
• Drive architecture selection and optimization for multi-die packages (2.5D/3D, HBM, interposers, silicon bridges, high-density substrates).
• Lead chip-package-board co-design: floorplan, die partitioning, bump maps, HBM/chiplet placement, pinout, routing, PDN, and board escape.
• Define package electrical requirements for high-speed interfaces (HBM, UCIe, PCIe, DDR, SerDes) and ensure SI/PI targets are met.
• Manage thermal-mechanical co-design and reliability risk mitigation for large, high-power packages.
• Establish and improve package design methodology, CAD infrastructure, automation, DRC/DFM/ERC signoff, and release processes.
• Lead technical engagement with foundries, OSATs, substrate suppliers, and EDA vendors to qualify technologies and support production ramp and yield improvement.
• Develop package technology roadmaps aligned with product plans and represent package engineering in program and executive reviews.

Requirements

Must-have technical skills and experience (education requirements are summarized separately under Education Requirements):

• Proven leadership of advanced package design or architecture teams; ability to hire, mentor, and build technical leadership capacity.
• Deep expertise in advanced semiconductor packaging for AI/HPC/server/networking products, including multi-chiplet 2.5D/3D integration, HBM, interposers, bridges, and high-density substrates.
• System-level understanding of chip-package-board interactions and the ability to translate product goals into package requirements.
• Expertise in package architecture and physical design: die/HBM placement, bump planning, pinout, routing topology, layer-stack optimization, PDN planning, and manufacturability.
• Strong competency in package SI/PI and electromagnetic analysis for high-speed I/O and power delivery; familiarity with transmission-line behavior, crosstalk, S-parameters, RLGC, and PDN impedance.
• Working knowledge of thermal-mechanical design, warpage, stress, assembly interactions, and package qualification considerations.
• Experience with industry EDA/package tools such as Cadence APD/SiP or Siemens Xpedition Package Designer and with SI/PI/extraction tools (e.g., XtractIM, PowerSI, HFSS, Q3D) or equivalents.
• Proven ability to define and deploy design methodologies, automation, verification strategies, metrics, and continuous-improvement initiatives.
• Excellent executive communication, cross-functional influence, and experience working with foundries, OSATs, substrate suppliers, and EDA partners.

Nice-to-have:

• Experience with Calibre or equivalent physical-verification tools and establishing package signoff criteria.
• Record of innovation (patents, publications, standards engagement) and prior experience leading large global organizations or multi-product programs.

Education Requirements

Minimum/acceptable credentials: Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field with 8+ years of relevant System/Package Design/Technology Engineering experience; OR Master's degree in those fields with 7+ years; OR PhD in those fields with 6+ years. Preferred: Master's or PhD with 15+ years of semiconductor/packaging experience. Relevant fields mentioned include Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering or related technical disciplines. Equivalent industry experience may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.