P&R Implementation Senior Staff Engineer

Job Title

P&R Implementation Senior Staff Engineer

Role Summary

Lead physical implementation for foundry testchips and 3DIC solutions, from floorplan through tapeout. Work across Synopsys product teams, foundry partners, and customer design teams to validate advanced process technologies and ensure robust, deployable implementation flows.

This is a hands-on engineering role focused on advanced-node P&R, signoff, and PPA optimization using Synopsys tooling and foundry PDKs.

Experience Level

Senior - 8+ years of hands-on physical design experience.

Responsibilities

Core responsibilities include technical ownership of testchip implementation, foundry enablement, and cross-team coordination.

• Drive foundry testchip projects from floorplan through tapeout and validate new process technologies.
• Develop and refine foundry implementation and 3DIC solutions aligned with Synopsys reference methodology.
• Provide hands-on engineering support to foundry partners and customers on DTCO, PPA optimization, and testchip bringup.
• Debug complex P&R, timing, and physical verification issues across multi-die and advanced packaging contexts.
• Coordinate with foundries, internal product teams, and customer design teams to resolve implementation flow bottlenecks and drive tool adoption.
• Collaborate with field account and jumpstart teams to support customer engagements and accelerate tool deployment.
• Implement productivity improvements via automation, scripting, and AI-assisted engineering tools.
• Mentor engineering teams and feed real-world learnings back into product and methodology teams.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• Deep expertise in place-and-route methodology, top-level implementation, and P&R timing signoff using Synopsys Fusion Compiler.
• Proven experience in high-performance and low-power physical design, including full-chip PPA optimization and design closure.
• Hands-on experience with signoff and analysis tools such as PrimeTime, StarRC, IC Validator, and RedHawk (or equivalents).
• Track record contributing to real SoC, CPU, or GPU tapeouts, ideally on advanced nodes (7nm or below).
• Strong debugging and problem-solving skills for complex timing, DRC, LVS, and IR drop issues.
• Experience working with foundry PDKs and design rule decks.
• Ability to communicate effectively with foundry engineers, product managers, and customer design teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering. The posting specifies 8+ years of hands-on physical design experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.