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NPU STA/Timing Engineer (Senior/Lead)

Qualcomm
August 31, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Senior

Job Title

NPU STA/Timing Engineer (Senior/Lead)

Role Summary

Join Qualcomm's hardware engineering team to drive static timing analysis (STA) and timing convergence for NPU/multi‑voltage domain ASIC designs. The role focuses on timing signoff, validation across PVT corners, tool/methodology development, and cross‑functional collaboration with physical design and technology teams.

Experience Level

Senior / Lead — typically 3–10 years of STA/timing or back‑end physical design experience; specific minimums vary by degree (see Education Requirements).

Responsibilities

Primary responsibilities include timing analysis, convergence, and methodology work for chip and hard‑macro designs.

  • Set up STA flows, drive timing convergence, perform reviews and signoff for multi‑mode, multi‑voltage designs.
  • Perform timing analysis, validation and debug across multiple PVT conditions using PrimeTime and/or Tempus.
  • Run PrimeTime/Tempus for STA flow optimization and correlate Spice to STA results.
  • Evaluate timing methodologies and tools across designs and technology nodes.
  • Develop automation and methodology scripts within STA/PD tool environments.
  • Collaborate with physical design, circuit simulation and silicon teams to resolve timing, SI, and correlation issues.
  • Prepare clear technical documentation and communicate findings with cross‑functional teams.

Requirements

Key technical skills and experience required for successful performance in the role.

  • Proven STA/timing experience (preferred 3–10 years) including timing convergence at chip and hard‑macro level.
  • Hands‑on experience with STA tools: PrimeTime and/or Tempus.
  • Strong understanding of timing concepts: AOCV/POCV, CTS, timing constraints, latch transparency, 0‑cycle and multi‑cycle paths.
  • Experience with design implementation and back‑end flows and tools (ICC / Innovus / Innovous reference familiarity).
  • Familiarity with circuit simulation and process enablement: HSpice / FineSim and Monte Carlo correlation to silicon.
  • Proficient scripting for automation: TCL, Perl, Python (Awk experience noted).
  • Knowledge of signal integrity, crosstalk, parasitic extraction and feed‑through handling.
  • Clear technical writing and communication skills; able to work collaboratively across teams.
  • Basic understanding of device physics.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. The posting specifies degree+experience combinations: Bachelor's + ≥3 years, Master's + ≥2 years, or PhD + ≥1 year. It also references B.Tech / MTech / MS in Electrical / Electronics / Microelectronics / VLSI. (Equivalent practical experience implied by the degree+experience structure.)


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-08-29