NPU/AI Processor Synthesis Staff Engineer
QualcommJob Title
NPU/AI Processor Synthesis Staff Engineer
Role Summary
Lead synthesis and timing-closure efforts for Neural Processing Unit (NPU) IP and subsystems in SoC projects. Collaborate with architecture, RTL, STA and physical design teams to deliver optimized gate-level netlists for advanced process nodes.
Responsible for synthesis flow development, PPA optimization, constraint management, quality checks, and mentoring synthesis engineers.
Experience Level
Senior. The posting prefers extensive experience (example guidance: 15+ years in ASIC synthesis and timing closure, including at least 3 years on NPU/AI processor design). Minimum qualifications also list degree-dependent experience alternatives (Bachelor's +4 years, Master's +3 years, PhD +2 years).
Responsibilities
Core responsibilities include owning synthesis flows, driving timing closure, and coordinating cross-functional handoffs.
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using Synopsys Design Compiler and Cadence Genus.
- Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
- Drive pre-layout and post-layout timing closure across voltage and process corners; collaborate with STA teams to resolve violations.
- Apply physical-aware synthesis and low-power techniques (UPF/CPF) to meet PPA targets.
- Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.
- Perform LEC, clock/power checks, linting, and other QoR analyses.
- Explore advanced synthesis methodologies and EDA tool capabilities to improve QoR.
- Mentor junior engineers and promote synthesis and timing best practices across teams.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Extensive hands-on experience in ASIC design flow: RTL → synthesis → STA → P&R, focused on synthesis and timing closure.
- Proficiency with synthesis tools (Synopsys Design Compiler, Cadence Genus) and STA tools (Synopsys PrimeTime).
- Experience with UPF/CPF low-power flows and multi-voltage designs.
- Advanced scripting skills for automation (Tcl, Perl, Python).
- Familiarity with static-analysis and verification tools (Spyglass, lint, CDC tools) and power analysis tools.
- Proven ability to lead teams and coordinate across RTL, DFT, STA, and physical design disciplines.
- Hands-on experience diagnosing and resolving setup/hold violations and improving QoR.
Nice-to-have:
- Experience at advanced process nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.
- Prior tape-out experience for NPU, DSP, or similar cores.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related technical field. The posting specifies degree-dependent minimum experience: Bachelor's +4 years, Master's +3 years, or PhD +2 years. The role also references a preference for deep domain experience (example: 15+ years) in ASIC synthesis and timing closure with multi-year experience on NPU/AI processors.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
