NPU/AI Processor Synthesis - Principal Engineer/Manager
QualcommJob Title
NPU/AI Processor Synthesis - Principal Engineer/Manager
Role Summary
Lead synthesis and timing-closure activities for NPU/AI processor IP and subsystems in advanced SoCs. Drive synthesis flows and PPA (performance, power, area) optimization while coordinating with architecture, RTL, STA and physical design teams.
Experience Level
Senior (Principal/Manager level). Prefer candidates with extensive ASIC synthesis experience — typically 15+ years in synthesis and timing closure, including at least 3 years working on NPU or AI processor design.
Responsibilities
Accountable for synthesis, timing-quality, and handoff of NPU IP and subsystems; lead and improve synthesis flows and mentor team members.
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry tools (e.g., Synopsys Design Compiler, Cadence Genus).
- Develop and maintain synthesis scripts and hierarchical/flat flows; automate flows with scripting.
- Drive pre-layout and post-layout timing closure across voltage and process corners; work with STA teams to resolve setup/hold violations.
- Apply physical-aware synthesis and low-power strategies (UPF/CPF, multi-voltage) to meet PPA targets.
- Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle and false paths.
- Perform quality checks including LEC, clock/power checks, linting, CDC analysis.
- Collaborate with RTL, DFT and physical design teams and provide feedback to improve QoR.
- Mentor junior engineers and promote synthesis/timing best practices.
Requirements
Must-have technical skills and demonstrable synthesis/timing experience. Education details are listed under Education Requirements below.
- Must-have: Strong knowledge of the ASIC design flow: RTL → synthesis → STA → P&R.
- Must-have: Proficiency with synthesis tools (Synopsys Design Compiler, Cadence Genus) and STA tools (PrimeTime).
- Must-have: Hands-on timing-closure experience across multiple corners and process-voltage conditions.
- Must-have: Experience with UPF/CPF-based low-power flows and multi-voltage designs.
- Must-have: Scripting and automation skills (Tcl, Perl, Python).
- Must-have: Familiarity with EDA signoff and checking tools (Spyglass, Lint, CDC tools, power analysis).
- Must-have: Proven leadership: leading synthesis efforts, coordinating cross-functional teams, and mentoring engineers.
- Nice-to-have: Experience with advanced process nodes (5nm/3nm), hierarchical synthesis, physical-aware flows and prior tape-out experience for NPU or DSP cores.
Education Requirements
Degree preferred: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering or related engineering/technical field. Employer-specified minimums: Bachelor's +6 years, Master's +5 years, or PhD +4 years of relevant hardware engineering experience. The role additionally prefers extensive ASIC synthesis experience (typically ~15+ years) with at least 3 years in NPU/AI processor design.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
