NPU/AI Processor Synthesis Lead (Staff / Sr Staff / Technical Lead)
QualcommJob Title
NPU/AI Processor Synthesis Lead (Staff / Sr Staff / Technical Lead)
Role Summary
Lead synthesis and timing-closure efforts for Neural Processing Unit (NPU) IP and subsystems within advanced SoCs. Work across architecture, RTL, static timing analysis, and physical design teams to produce high-quality gate-level netlists optimized for performance, power, and area.
Experience Level
Senior — role expects significant domain experience: typically 15+ years in ASIC synthesis and timing closure, with at least 3 years working on NPU or AI processor design.
Responsibilities
Accountable for end-to-end synthesis and timing quality for NPU IP and subsystems and for leading a synthesis team.
- Own RTL-to-gate-level synthesis using industry tools (e.g., Synopsys Design Compiler, Cadence Genus) and maintain synthesis flows and scripts.
- Drive pre-layout and post-layout timing closure across voltage/process corners; collaborate with STA to resolve setup/hold issues.
- Apply physical-aware synthesis and low-power strategies (UPF/CPF, multi-voltage) to meet PPA targets.
- Validate and maintain SDC constraints for clocks, I/O, multi-cycle and false paths.
- Perform quality checks including LEC, clock/power checks, linting, and other verification steps.
- Collaborate with RTL, DFT and physical design teams; provide QoR feedback to architecture and RTL teams.
- Investigate and adopt advanced synthesis methodologies and EDA tool capabilities to improve results.
- Mentor and lead junior engineers; drive best practices across synthesis and timing teams.
Requirements
Must-have technical skills and senior-level experience required for this position. Education credentials are summarized separately under Education Requirements.
- 15+ years in ASIC synthesis and timing closure with at least 3 years focused on NPU or AI processor design.
- Deep knowledge of the ASIC flow: RTL → synthesis → STA → place & route and timing signoff practices.
- Proven proficiency with synthesis tools (Synopsys Design Compiler, Cadence Genus) and STA tools (PrimeTime).
- Experience with UPF/CPF flows and implementing low-power, multi-voltage designs.
- Strong scripting skills for automation (Tcl, Perl, Python).
- Familiarity with EDA analysis tools (Spyglass, lint/CDL tools, CDC tools, power analysis).
- Experience with SDC constraint creation/validation and resolving cross-domain timing issues.
- Experience with physical-aware synthesis and working for advanced process nodes (preferred: 5nm/3nm) and tape-out cycles.
- Demonstrated leadership: mentoring engineers and coordinating cross-functional teams.
Education Requirements
Posting specifies degree-based minimums: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering, Computer Engineering or related field with 4+ years of hardware engineering experience; OR Master's in those fields with 3+ years; OR PhD in those fields with 2+ years. The posting also lists senior-level experience expectations (15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU/AI processor design).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
