NOC DV Engineer

Job Title

NOC DV Engineer

Role Summary

Design Verification (DV) engineer responsible for leading verification of complex NoC, interconnect, AI, networking, datacenter, and HPC IPs or sub-systems. The role owns verification from specification review through signoff-quality closure and works with cross-functional teams to ensure protocol, performance, and system-level correctness.

Experience Level

Mid-level - typically 3+ years of relevant hardware/DV experience (see Education Requirements for degree-equivalent alternatives).

Responsibilities

Core responsibilities include planning and executing verification campaigns, building reusable verification environments, and driving closure to signoff.

• Own IP/sub-system DV from spec review to verification closure and signoff.
• Design and build reusable SystemVerilog/UVM environments, UVCs/agents, sequences, scoreboards, checkers, and coverage infrastructure.
• Develop constrained-random tests, assertions (SVA), functional coverage models, and regression suites.
• Perform root-cause analysis and debug across RTL, protocol, architecture, performance, and testbench issues.
• Develop automation for regressions and CI/CD workflows; integrate simulators, emulation, and verification tools.
• Validate performance, QoS, congestion, and scalability; participate in system-level qualification and post-silicon correlation where applicable.
• Collaborate with architects, RTL designers, software, and validation teams; provide technical leadership and execution in fast-paced projects.

Requirements

Must-have technical skills and experience to perform the role; preferred items are listed separately.

• Expert knowledge of SystemVerilog and UVM; experience building verification environments and components.
• Strong experience with constrained-random verification, SVA, functional coverage closure, regression management, and signoff methodologies.
• Protocol verification experience with one or more high-speed protocols (PCIe, USB, Ethernet, CXL, or similar).
• Experience verifying NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data-movement fabrics.
• Proficiency in scripting/automation (Python, Shell, Perl, or Tcl) for regression and infrastructure development.
• Familiarity with industry-standard simulators, debug/coverage tools, emulation/prototyping, and CI/CD verification workflows.
• Strong debugging, root-cause analysis, and performance verification skills (QoS, congestion, scalability).
• Excellent collaboration and communication skills; ability to lead technical efforts and deliver results independently.

Education Requirements

Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, VLSI, or a related engineering field. Typical minimums listed: Bachelors + 3+ years, Masters + 2+ years, or PhD + 1+ year of relevant hardware/DV experience. The posting also references B.Tech/M.Tech from reputed institutions (IITs, NITs, IIITs, BITS) as examples. Equivalent practical experience is acceptable where stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.