NOC Design Verification Staff Engineer

Job Title

NOC Design Verification Staff Engineer

Role Summary

Responsible for verification of next-generation infrastructure IPs (e.g., DDR, memory controllers) that integrate into SoCs. Plan and implement IP/cluster/formal verification flows, own DV testbench and verification collateral, and coordinate with design, SoC, emulation, and silicon teams to achieve quality sign-off.

Experience Level

Senior — typically requires substantial experience in IP verification (commonly 8+ years in IP verification or related roles).

Responsibilities

Key responsibilities include:

• Own and maintain DV testbench and verification collateral (checkers, trackers, scoreboards, assertions, functional coverage).
• Develop verification plans and test cases to cover feature sets and drive coverage closure across levels of testing.
• Implement IP/cluster/formal verification flows and deploy verification tools (e.g., Certitude, VC Formal, VPlan).
• Collaborate with system architects, RTL designers, emulation and SoC teams on failure analysis and debug.
• Analyze regression results, debug signatures, and identify/follow up on bug fixes.
• Participate in post-silicon debug and root-cause analysis with design, software, and test teams.
• Support SoC-level performance modeling on latency and bandwidth analysis as required.
• Prepare and maintain verification documentation required for quality sign-off.

Requirements

Must-have technical skills and experience:

• Proven expertise in UVM-based verification and SystemVerilog.
• Experience developing monitors, scoreboards, sequencers and verification infrastructures to accelerate bug discovery and resolution.
• Familiarity with ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Strong debugging, analytical and problem-solving skills; experience debugging regressions and silicon issues.
• Experience working across large, distributed engineering teams and communicating with stakeholders.
• Experience with verification automation and scripting; familiarity with tools such as Certitude, VC Formal, VPlan.
• Experience with post-silicon bring-up and HW-SW debug is highly desirable.

Nice-to-have:

• Experience with low-power design verification (dynamic clock gating, power collapse techniques).
• Experience verifying designs to Automotive Safety Integrity Levels (ASIL).
• Proficiency in Python/Perl for automation and C/C++/SystemC for performance modeling.
• Exposure to silicon debug toolchains and SoC-level performance modeling.

Education Requirements

Minimum qualifications reference academic degrees: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics, Engineering, or a related field (with degree-dependent experience expectations listed by the employer). Additionally, a separate qualification line cites a preference for 8+ years of IP verification experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.