NOC Design Verification Staff Engineer

Job Title

NOC Design Verification Staff Engineer

Role Summary

Lead verification architect/engineer responsible for planning and executing verification for Infrastructure IPs (DDRSS, memory controllers, etc.) used in SoCs. Collaborate with design, SoC, emulation, and post-silicon teams to close coverage, debug issues, and deliver verification sign-off.

Experience Level

Senior level. The posting expects experienced candidates (examples in the source reference 8 years in IP verification; minimum qualifications also list degree-dependent experience ranges).

Responsibilities

Core responsibilities include ownership of IP verification flows and coordination across teams.

• Own DV testbench and verification collateral: checkers, trackers, scoreboards, assertions, functional coverage.
• Develop verification test plans and test cases; drive code and functional coverage closure.
• Plan and implement IP/cluster/formal verification flows and associated scripts/tools (e.g., Certitude, VC Formal, VPlan).
• Debug regression failures, identify/fix bugs, and collaborate with System Architects, Design, and emulation teams on failure analysis.
• Perform post-silicon debug and root-cause analysis with design, software, and test teams.
• Coordinate with SoC-level performance modeling on latency and bandwidth analysis.
• Prepare verification quality sign-off and required documentation.

Requirements

Required technical skills and experience (must-haves first; desirable items listed last).

• Must-have: Strong debugging, analytical, and problem-solving skills.
• Must-have: Expertise with UVM-based verification and SystemVerilog testbench components (monitors, scoreboards, sequencers).
• Must-have: Knowledge of ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Must-have: Experience developing automation scripts and tools; proficiency in at least one scripting language (Python or Perl) preferred for automation.
• Must-have: Effective communication and collaboration skills to work with large, distributed design organizations.
• Nice-to-have: Experience with low-power design techniques (dynamic clock gating, memory power collapse) and ASIL/automotive safety verification.
• Nice-to-have: Familiarity with C/C++/SystemC for performance models and exposure to post-silicon bring-up and silicon debug tool chains.

Education Requirements

Degrees: Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics, or related engineering fields. The posting specifies degree-dependent experience guidance (e.g., Bachelors +4+ years, Masters +3+ years, PhD +2+ years) and also references 8 years of IP verification experience in a separate qualification line. Equivalent practical experience may be considered where noted.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.