NOC Design Verification Senior Engineer
QualcommJob Title
NOC Design Verification Senior Engineer
Role Summary
Lead design verification for complex interconnect, networking, datacenter, HPC and AI accelerator IPs and sub-systems. Drive verification from architecture and specification through sign-off-quality closure, collaborating with cross-functional SoC teams.
Experience Level
Senior level. Position expects demonstrated, independent ownership of complex IP/sub-system verification programs; see Education Requirements for degree/years guidance.
Responsibilities
The role owns verification planning, implementation, and closure for NoC/interconnect and related IPs. Key duties include:
- Lead DV activities from spec review to verification closure and signoff.
- Architect and implement reusable SystemVerilog/UVM environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.
- Develop and execute constrained-random verification, SVA usage, functional coverage closure, and regression management.
- Debug RTL, protocol, architecture, performance, and testbench issues; perform root-cause analysis and corrective actions.
- Verify NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, and complex data-movement fabrics.
- Perform protocol-specific verification and validation for high-speed interfaces and system-level qualification.
- Develop automation and regression infrastructure using scripting and CI/CD tooling; use emulation/prototyping where applicable.
- Collaborate with architects, RTL designers, validation and software teams to ensure system-level correctness and performance.
Requirements
Must-have technical skills and experience for successful execution of the role.
- Expert in SystemVerilog and UVM with hands-on experience building reusable verification frameworks.
- Strong verification planning skills, including constrained-random methodologies, SVA, coverage closure, regression management, and signoff processes.
- Proven experience verifying NoC/interconnects, memory/cache subsystems, AI accelerators, or similar complex subsystems.
- Deep protocol verification expertise in one or more high-speed protocols (PCIe, USB, Ethernet, CXL, or similar).
- Solid understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.
- Strong RTL, protocol, architecture and testbench debugging capabilities and root-cause analysis.
- Proficiency in scripting for automation and infrastructure (Python, Shell, Perl, or Tcl).
- Familiarity with industry simulators, debug and coverage tools, emulation/prototyping, and CI/CD workflows.
- Effective collaboration, communication, technical leadership, and task execution in fast-paced environments.
Nice-to-have:
- Experience with SystemC/TLM, performance modeling, emulation/post-silicon correlation, or delivering first-pass verification closure for complex SoC platforms.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, VLSI, or a related engineering discipline. The posting specifies typical experience tied to degree level: Bachelors + ~3 years, Masters + ~2 years, PhD + ~1 year. B.Tech/M.Tech from strong engineering institutions (e.g., IITs/NITs/IIITs/BITS or equivalent) is highlighted.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
