NoC Design Verification Engineer

Job Title

NoC Design Verification Engineer

Role Summary

Responsible for planning and executing functional verification for Network-on-Chip (NoC) and coherent interconnect IP/subsystems. Work on UVM/SystemVerilog verification environments, assertions, coverage, and subsystem integration while collaborating with design and architecture teams in Ahmedabad.

Experience Level

Mid-level (4+ years of design verification experience).

Responsibilities

Key responsibilities include:

• Develop and execute verification plans for NoC and coherent interconnect IP/subsystems.
• Design and implement UVM/SystemVerilog verification environments, testbenches, checkers, scoreboards, and functional coverage.
• Create assertions (SVA), checkers, and coverage aligned to NoC specifications and configurations.
• Verify multiple NoC configurations, topologies, routing scenarios, and protocol interactions.
• Drive subsystem integration verification involving memory fabrics, cache/coherency paths, and large SoC interconnects.
• Debug simulation failures, isolate root cause, and coordinate fixes with RTL/design teams.
• Track verification progress using coverage, bug trends, and testplan completion metrics; support regression bring-up and test triage.
• Contribute reusable VIP/interfaces and DV components for interconnect verification.

Requirements

Must-have skills and experience:

• 4+ years of industry experience in design verification.
• Strong experience with SystemVerilog and UVM.
• Experience verifying interconnects, NoCs, memory subsystems, cache/coherency logic, or large SoC subsystems.
• Proficient in verification methodologies: constrained-random, test planning, assertions, coverage, and regression debug.
• Experience writing SVA/assertion-based checks and functional coverage models.
• Strong RTL, testbench, and simulation debugging skills; solid understanding of computer architecture and on-chip data movement.

Nice-to-have:

• Experience with coherent interconnects, NoC or memory fabrics, and subsystem- or SoC-level verification.
• Familiarity with VIP/interface development and protocol compliance checking.
• Exposure to performance, stress, corner-case, and configuration-based verification.
• Scripting experience in Python, Perl, or shell; exposure to formal verification or CDC planning.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. The role expects approximately 4+ years of relevant design verification experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.