NoC Design Verification Engineer

Job Title

NoC Design Verification Engineer

Role Summary

The NoC Design Verification Engineer will plan and execute verification for NoC and coherent interconnect IP/subsystems. The role works within the verification team to build UVM/SystemVerilog environments, verify multiple NoC configurations and integrations, and drive closure with RTL and architecture teams.

Experience Level

Mid-level — typically requires 4+ years of relevant industry experience in design verification or related roles.

Responsibilities

Primary responsibilities include designing and running verification flows, debugging failures, and collaborating with design and architecture teams to ensure correct interconnect behavior.

• Develop and execute verification plans for NoC and coherent interconnect IP/subsystems.
• Build UVM/SystemVerilog verification environments, testbenches, checkers, scoreboards, assertions, and functional coverage.
• Verify multiple NoC configurations, topologies, routing scenarios, and protocol interactions.
• Create and maintain assertions, checkers, and coverage aligned with NoC specifications and configurations.
• Drive verification of subsystem integration involving memory fabrics, cache/coherency paths, and large SoC interconnects.
• Partner with design and architecture teams to convert specifications into actionable test plans.
• Debug simulation failures, isolate root causes, and coordinate fixes with RTL/design teams.
• Track verification progress using metrics such as coverage, bug trends, and testplan completion.
• Contribute to VIP/interface development and reusable DV components; support regression bring-up and verification closure.

Requirements

Must-have technical skills and experience, followed by desirable skills that improve effectiveness in this role.

• 4+ years of industry experience in design verification.
• Strong experience with SystemVerilog and UVM-based verification.
• Experience verifying interconnects, NoCs, memory subsystems, cache/coherency logic, or large SoC subsystems.
• Solid understanding of verification methodologies: test planning, constrained-random verification, assertions, coverage, and regression debug.
• Experience writing SVA/assertion-based checks and functional coverage models.
• Strong debugging skills across RTL, testbench, and simulation environments.
• Good understanding of computer architecture and on-chip data movement.
• Nice-to-have: experience with coherent interconnects, NoC/memory fabrics, VIP/interface verification and VIP development.
• Nice-to-have: scripting experience (Python, Perl, shell); exposure to subsystem/SoC-level verification, performance/stress/corner-case verification, formal or CDC verification.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.