NOC Design - Senior Engineer
QualcommJob Title
NOC Design - Senior Engineer
Role Summary
Senior verification engineer responsible for planning and implementing verification flows for infrastructure IPs (e.g., DDRSS, memory controllers) that go into SoCs. The role partners with design, SoC, emulation and bring-up teams to verify functionality, close coverage, debug silicon issues and deliver production-quality IP.
Experience Level
Senior — this role targets experienced engineers. The posting indicates a preference for senior-level experience (examples include an explicit 8+ years preference in qualifications). The hiring bar also lists alternative minimums tied to degree level (see Education Requirements).
Responsibilities
Key responsibilities for this position include ownership of verification collateral, coordinating with cross-functional teams, and driving quality to sign-off.
- Own DV testbench and verification collateral: checkers, trackers, scoreboards, assertions, functional coverage.
- Plan and implement IP/cluster/formal verification flows and develop test plans and test cases to exercise features and meet coverage goals.
- Coordinate with system architects, design, emulation and SoC teams during development and bring-up.
- Debug regression failures, identify root causes and follow through on fixes.
- Produce quality sign-off artifacts and required verification documentation.
- Develop and deploy automation, scripts and tools to support validation and flow execution.
- Collaborate on post-silicon debug and root-cause analysis with design, software and test teams.
- Work with SoC performance modeling teams on latency and bandwidth analysis.
Requirements
Concise list of required and preferred technical skills. Degree requirements are summarized separately under Education Requirements.
- Must-have: Strong debugging, analytical and problem-solving skills.
- Expertise in UVM-based verification and experience developing monitors, scoreboards and sequencers using SystemVerilog/UVM.
- Experience verifying infrastructure IPs such as DDRSS and memory controllers; ability to plan IP and cluster verification flows.
- Familiarity with ARM bus protocols, virtual memory concepts and SoC system architecture.
- Experience with regression debug, code/functional coverage closure and quality sign-off processes.
- Good communication and collaboration skills to work with large, distributed design organizations.
- Nice-to-have: Experience with low-power design techniques (clock gating, power collapse), ASIL/automotive verification, scripting for automation (Python, Perl), C/C++/SystemC for performance models, post-silicon bring-up and silicon debug toolchains.
Education Requirements
Degrees: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics or related engineering fields. The posting specifies degree-plus-experience combinations: Bachelor's + 4 years; Master’s + 3 years; PhD + 2 years. A separate qualification line also notes a preference/requirement for ~8 years of IP verification or related experience for this role.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
