NoC Architect (Network on Chip)
Volantis SemiconductorJob Title
NoC Architect (Network on Chip)
Role Summary
Architect responsible for the design and ownership of the on‑chip network (NoC) inside the XPU and its integration with the broader system and inter‑chip networks.
Work with SoC architects, verification teams, and system engineers to define NoC topology, performance targets, integration points, and IP strategy.
Experience Level
Senior-level architect. Specific years of experience not stated; role requires substantial hands-on NoC architecture, design, and verification experience.
Responsibilities
Primary responsibilities include:
- Define and own NoC architecture, topology, protocols, and interfaces for the XPU.
- Drive integration of the NoC with cores, accelerators, memory subsystems, and chip-to-chip links.
- Evaluate and recommend build vs. buy decisions for NoC IP and document trade-offs.
- Define and lead verification strategy for NoC and IP integration.
- Collaborate with system, hardware, firmware, and verification teams to meet performance, power, and area goals.
- Provide technical leadership in design reviews and mentor engineering team members.
Requirements
Must-have and preferred technical qualifications:
- Must-have: Hands-on experience designing, integrating, and verifying NoCs.
- Must-have: Experience deciding on build vs. buy for NoC IP and justifying the decision.
- Must-have: Experience in verification focused on NoC and IP integration.
- Nice-to-have: Experience with chip-to-chip networks and NoCs that act as chip-to-chip switches (e.g., TPU or Anton style).
- Nice-to-have: Experience with direct-connect networks that use NoCs for switching.
Education Requirements
Not specified.
About the Company
Company: Volantis Semiconductor
Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.
