Next-Gen High-Speed HBM/LPDDR Memory Subsystem ASIC Digital Design Engineer

Job Title

Next-Gen High-Speed HBM/LPDDR Memory Subsystem ASIC Digital Design Engineer

Role Summary

Design and deliver front-end digital logic for high-speed memory subsystems (HBM, LPDDR, DDR) used in Qualcomm QCT products. Work covers architecture, RTL implementation, timing closure, and support through integration into system-on-chip products.

Experience Level

Senior-level. The posting requests experienced engineers (typical guidance: 5+ years ASIC design experience and 3+ years hardware architecture experience; minimum experience alternatives apply depending on degree).

Responsibilities

Primary responsibilities include design, implementation, and delivery of high-speed memory subsystem RTL and support through integration and silicon bring-up.

• Define and drive micro-architecture and detailed RTL for memory controllers, caches, and NoC front-ends.
• Implement RTL, deliver synthesizable code, and coordinate with verification teams to ensure functional quality.
• Perform synthesis, timing closure, and provide physical design support during place-and-route.
• Run and analyze gate-level simulations and power analysis; iterate on design based on results.
• Debug logic at IP and full-chip integration level and support system-level bring-up.
• Contribute to design methodology and process improvements to increase productivity and quality.

Requirements

Key technical skills and experience required or strongly preferred. Degree specifics are summarized under Education Requirements below.

• Must-have: 5+ years of ASIC RTL/front-end digital design experience and 3+ years of hardware architecture experience; proven experience with high-speed (1+ GHz) designs.
• Must-have: Strong RTL coding skills and experience collaborating with verification and physical design teams.
• Must-have: Experience with synthesis, timing closure, gate-level simulation, and power analysis workflows.
• Preferred: Experience with LPDDR memory controllers, cache controller architecture, NoC-based front-end designs, and exposure to HBM designs.
• Preferred: Familiarity with x86 or ARM CPU/bus architectures and techniques for ordering memory transactions to meet ISA requirements.
• Nice-to-have: Familiarity with RTL verification flows, on-chip SRAM/L3 controller design, and tools commonly used in high-speed ASIC design.

Education Requirements

Required: Bachelor's degree in Computer Engineering, Electrical Engineering, Science, Engineering, or a related field. Preferred: Master's degree in Computer Engineering or Electrical Engineering. Alternate qualification paths accepted: Master's degree plus 3+ years of related ASIC work, PhD plus 2+ years, or Bachelor's plus 4+ years of related experience.

For more information about Qualcomm, see Qualcomm contact.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.