Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Job Title

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Role Summary

Design and deliver RTL and microarchitecture for high-speed memory subsystems (HBM/LPDDR/DDR) and NoC front-ends used in SoCs. Work on architecture, RTL implementation, synthesis/timing closure, and integration support for Qualcomm QCT products.

Collaborate with verification, physical design, and system teams to debug integrations, optimize performance and power, and improve design methodology.

Experience Level

Senior — typically 5+ years of ASIC/front-end digital design experience and 3+ years of hardware architecture experience.

Responsibilities

Deliver architecture, RTL, and integration-ready designs for memory subsystem logic and related interfaces.

• Define and drive micro-architecture and design specifications for memory controllers and front-end NoCs.
• Implement RTL, perform synthesis and timing closure, and support physical design and gate-level simulations.
• Collaborate with verification teams to ensure quality and completeness of coverage and debug issues raised by verification and integration.
• Analyze power and performance; optimize implementations for high-speed (1 GHz+) operation.
• Provide debug support during chip integration and system bring-up.
• Contribute to design methodology improvements and productivity initiatives.

Requirements

Must-have technical skills and experience for successful performance in the role.

• 5+ years ASIC design experience with RTL coding and front-end digital design.
• 3+ years of hardware architecture experience driving micro-architecture decisions.
• Experience enabling high-speed designs (1 GHz+), including synthesis and timing closure workflows.
• Experience with LPDDR memory and cache controller design and NoC front-end architectures interfacing to CPU/DSP/multimedia processors.
• Experience with on-chip tightly coupled SRAM and L3 cache controller architecture/design.
• Familiarity with x86 or ARM CPU and bus architectures and memory transaction ordering to meet ISA requirements.
• Skills in RTL debug, gate-level simulation, power analysis, and providing integration/debug support.
• Preferred: exposure to HBM-type designs and RTL design verification flows; broad ASIC design experience (3–10 years is common for candidates).

Education Requirements

Required: Bachelor's degree in Science, Engineering, Computer Engineering or Electrical Engineering (or related field). Preferred: Master's degree in Computer Engineering or Electrical Engineering. The posting also lists alternate qualification paths: Master's + 3+ years experience, or PhD + 2+ years experience, and allows related technical fields or equivalent practical experience in lieu of a listed degree.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.