Network-on-Chip / Interconnect Design Staff Engineer

Job Title

Network-on-Chip / Interconnect Design Staff Engineer

Role Summary

Design and architect Network-on-Chip (NoC) and interconnect fabrics for next-generation SoCs used in smartphones, notebooks, wearables and tablets. Own specification, micro-architecture, RTL design and verification activities for coherent and non-coherent interconnect IP.

Experience Level

Senior-level. The posting requires experienced engineers (typical expectation: 8+ years of IP/SoC design experience; see Education Requirements for degree-based experience alternatives).

Responsibilities

Work across architecture, design, verification and silicon teams to deliver interconnect IP and ensure performance and silicon correctness.

• Define architecture and micro-architecture for next-generation coherent and non-coherent interconnect fabrics.
• Specify, implement and verify interconnect IP (RTL and related blocks).
• Collaborate with SoC architecture, performance, physical design, floorplan, core teams and silicon validation.
• Ensure interconnect meets performance, timing and verification requirements; correlate pre-silicon assumptions with post-silicon behavior.
• Design and integrate debug hooks and observability for silicon bring-up and root-cause analysis.
• Manage SoC dependencies, plan front-end design tasks and drive project milestones across design, verification and physical implementation.
• Contribute as a core member of the NoC/Interconnect infrastructure team (BDC).

Requirements

Must-have technical skills and experience for immediate contribution.

• 8+ years of solid IP/SoC design experience in interconnect or related subsystems.
• Strong understanding of interconnect protocols and concepts (examples: CHI, AHB, AXI, ACE, ACE-Lite, NoC).
• Proven RTL development skills, including Verilog RTL coding and RTL-to-gates flow knowledge.
• Familiarity with multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.
• Experience with synthesis flows (Design Compiler / DC/DCG), timing closure and physical-design interactions.
• Practical knowledge of DFT, formal verification, silicon debug and common signoff checks (lint, CDC, PLDRC, CLP).
• Ability to plan, track and drive cross-team deliverables; strong communication and leadership skills.
• Nice-to-have: hands-on verification experience and formal verification project experience; prior work on SoC performance correlation and validation.

Education Requirements

Degrees cited: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related field. The posting lists multiple acceptable combinations of degree and experience: either 8+ years of IP/SoC design experience, or degree-based alternatives (Bachelor's + 4+ years hardware engineering experience; Master's + 3+ years; PhD + 2+ years). Equivalent practical work experience is accepted where listed.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.