Network Architect

Job Title

Network Architect

Role Summary

Lead the architecture, design, and implementation of an inter-wafer scale-up network that connects high-bandwidth, high-capacity wafers into a unified system for large-scale AI workloads. Work cross-functionally with silicon, systems, and software teams to define network topology, protocols, and reliability requirements.

Experience Level

Senior — architect-level role. Typically requires extensive networking experience (commonly 7+ years) and prior system- or chip-level design involvement.

Responsibilities

Lead technical activities and make architecture decisions for the inter-wafer network. Key responsibilities include:

• Design and evaluate network topologies and tradeoffs for AI workloads (latency, bandwidth, message size, hops).
• Specify and prototype network protocols and their implementations across switch/NIC/host components.
• Collaborate with silicon and system teams to integrate network functions into wafer-scale systems.
• Define reliability, availability, and serviceability (RAS) requirements for large-scale fabrics.
• Analyze performance, scalability, and failure modes; recommend mitigations and improvements.
• Document architecture, requirements, and validation plans; mentor other engineers on network design choices.

Requirements

Must-have and preferred qualifications.

• Must-have: Deep knowledge of network architectures and topology tradeoffs for different workloads.
• Must-have: Experience designing or implementing network protocols.
• Must-have: Strong understanding of AI workload network characteristics (e.g., message sizes, latency sensitivity, bandwidth needs).
• Nice-to-have: Hands-on experience with switch or NIC chip architecture and design.
• Nice-to-have: Prior work on AI cluster networks and protocol tradeoffs for AI applications.
• Nice-to-have: Experience with large-scale optical network fabrics and RAS challenges.

Education Requirements

Not specified.

About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.