NAND Design Rule Engineer, Process Integration

Job Title

NAND Design Rule Engineer, Process Integration

Role Summary

Support development and high-volume manufacturing of advanced 3D NAND technologies. Drive delivery of design rules and PDKs, manage DRC waivers and mask definitions, and coordinate across process integration, design, yield, and quality teams to meet R&D and production milestones.

Experience Level

Senior-level. See Education Requirements for degree-based years-of-experience guidance.

Responsibilities

Accountable for design-rule and PDK execution across R&D and production programs. Key duties include:

• Lead release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Partner with Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability.
• Ensure quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules and ensure targets are met through cross-team coordination.
• Maintain proactive communication with stakeholders and escalate issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document lessons to improve production parts in design.

Requirements

Must-haves describe technical skills and domain knowledge; preferred items noted separately.

• Hands-on experience with PDKs, design rules, and layout work; able to perform minor layout tasks.
• Proficiency with CAD tools such as Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE, or equivalents.
• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge.
• Proven ability to resolve complex technical issues and communicate clearly under pressure.
• Familiarity with 3D NAND process flow and major NAND components (bit-line sensing, word-line driver, data path, analog circuits).
• Experience with CAD group interactions, data post-processing, and transferring design database data to reticles.
• Preferred: prior R&D experience in NAND or other memory technologies.

Education Requirements

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years relevant experience; or Master’s degree with 8+ years; or Bachelor’s degree with 13+ years in the semiconductor industry (areas such as Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.