MTS Design Engineer, Bonding and Packaging

Job Title

MTS Design Engineer, Bonding and Packaging

Role Summary

Lead electrical, thermal, and thermo-mechanical design and characterization for advanced semiconductor packages (HBM, wafer-to-wafer, chip-on-wafer, flip‑chip, TSV). Work with global R&D, vendors, and manufacturing to convert multiphysics simulation and test data into practical design rules, qualification plans, and technology roadmaps.

Experience Level

Senior — 15–20 years of professional engineering experience, including at least 10 years of direct experience in electrical, thermal, and mechanical package analysis, modeling, and validation.

Responsibilities

Provide technical leadership in bonding and packaging design, simulation, and characterization across multiple technologies and disciplines.

• Maintain subject-matter expertise in advanced packaging technologies: HBM, W2W, COW, flip chip, TSV.
• Drive design improvements by modeling electrical parasitics, insertion loss, and impedance across materials, geometries, and environments.
• Lead thermal analysis and propose short- and long-term solutions to reduce thermal impedance.
• Perform Chip‑Package Interaction (CPI) studies for 2.5D/3D systems; validate mechanical and thermo‑mechanical models and derive design rules.
• Define and coordinate characterization and testing plans with vendors and labs to collect material and electrical data for simulations.
• Integrate AI/ML workflows into design evaluations and accelerate simulation-driven decision making.

Requirements

Must-have technical experience and skills to perform the role; preferred items listed separately.

• Must-have: 15–20 years of professional engineering experience with at least 10 years of direct package analysis, modeling, and validation in the semiconductor industry.
• Must-have: Deep understanding of thermal performance drivers and contribution of each package layer to total thermal impedance.
• Must-have: Experience capturing multiphysics mechanisms in simulation (electrical, thermal, mechanical) and translating results into design guidance.
• Must-have: Proficiency with Design of Experiments (DOE) and statistical analysis tools (e.g., JMP or equivalent).
• Must-have: Demonstrated ability to integrate AI/ML and generative AI into engineering workflows and technical assessments.
• Nice-to-have: Signal integrity experience for high-speed package designs and characterizations.
• Nice-to-have: Familiarity with Cadence layout tools for reviewing test-vehicle designs.
• Nice-to-have: Data acquisition and numerical analysis skills (MATLAB, Excel, JMP, or similar).

Education Requirements

MS or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.