MTS – ASIC Device Technology & Silicon Yield Engineering
Micron TechnologyJob Title
MTS – ASIC Device Technology & Silicon Yield Engineering
Role Summary
Lead post-silicon yield, failure analysis, and RMA investigations for complex ASIC devices. Work with design, product engineering, test, foundry, and external partners to identify root causes, implement containment and corrective actions, and feed learning into future ASIC architecture and process improvements.
Experience Level
Senior — requires 12+ years of semiconductor industry experience.
Responsibilities
Accountable for technical leadership across post-silicon debug, failure analysis, and yield improvement.
- Lead end-to-end investigations of silicon yield loss, field returns, customer escalations, and reliability failures.
- Drive root-cause analysis across process, design, test, package, and system interactions; develop hypothesis-driven debug plans.
- Analyze device-level failure mechanisms and design–process interactions affecting analog, mixed-signal, memory, high-speed I/O, and PHY performance.
- Lead post-silicon debug for SRAM, PCIe PHY, ONFI, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems.
- Develop and execute silicon characterization plans and correlate electrical, yield, reliability, and FA data to isolate contributors.
- Oversee advanced failure analysis techniques (FIB, SEM/TEM, EFA, OBIRCH, LVP, emission microscopy, cross-section) and translate results into engineering actions.
- Implement containment, corrective actions, and preventive plans to improve yield and reduce repeat excursions.
- Lead technical reviews and present complex technical findings to cross-functional teams and executive leadership.
Requirements
Must-have qualifications and technical skills.
- 12+ years in the semiconductor industry with experience in advanced CMOS technology and silicon product development.
- Proven success leading yield improvement, RMA, and failure analysis efforts, including coordination with foundries and OSAT partners.
- Expertise in CMOS device physics, SRAM architecture, memory margin analysis, and failure mechanisms.
- Deep understanding of high-speed interfaces (PCIe, ONFI, LPDDR, SerDes), signal integrity, power integrity, and timing closure methodologies.
- Hands-on experience with post-silicon debug, characterization, process–design interaction analysis, and variation-aware design practices.
- Ability to correlate wafer acceptance test, electrical test, yield, reliability, failure analysis, and customer-return data to determine root cause.
- Strong communication and leadership skills to coordinate multi-functional teams and influence design and technology roadmaps.
Nice-to-have:
- Experience with SSD controller, AI accelerator, networking, or high-performance compute ASICs; AI/ML for yield analytics and anomaly detection.
- Experience mentoring teams and driving multi-site technical investigations.
Education Requirements
Ph.D. or M.S. in Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or equivalent practical experience.
About the Company
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.
