MTS ASIC Architect

Job Title

MTS ASIC Architect

Role Summary

The MTS ASIC Architect is a member of the DRAM ASIC Architecture team responsible for defining silicon-level architectures for DRAM products. The role provides architectural leadership across ASIC logic, DRAM die, packaging, and system integration to deliver high-bandwidth, energy-efficient, scalable, and reliable memory solutions.

Work spans near-term product execution and long-term technology direction with ownership of decisions affecting bandwidth density, latency, RAS, and system observability.

Experience Level

Mid-level / Member of Technical Staff. The posting requests extensive professional experience in DRAM die architecture but does not specify a numeric years-of-experience requirement.

Responsibilities

Primary responsibilities include architectural definition, cross-domain optimization, and technical leadership to ensure first-silicon success.

• Define ASIC and logic architectures to enable high data throughput, efficient parallelism, and scalable bandwidth delivery for advanced DRAM products.
• Drive architectural features that improve effective bandwidth, latency efficiency, and utilization under demanding workloads.
• Lead trade-off analyses across DRAM silicon, ASIC logic, packaging, power delivery, thermals, and signal integrity.
• Influence functional partitioning and interface definitions to optimize performance, power, and scalability.
• Perform architectural analysis including PPA evaluation, IO timing considerations, and scalability planning for next-generation products.
• Conduct micro-architectural, RTL, verification, and coverage reviews to mitigate risks and support first-silicon success.
• Provide technical leadership and mentorship to execution teams and influence cross-functional decisions through data-driven analysis.

Requirements

Must-have technical skills and experience required for successful performance in this role.

• Extensive professional experience in DRAM die architecture with deep understanding of trade-offs affecting bandwidth, latency, power efficiency, and reliability (RAS).
• Proven track record leading micro-architectural and architectural decisions for complex memory subsystems or silicon solutions from specification through product delivery.
• Experience performing architectural analyses (PPA, IO timing, scalability) and defining architectural guardrails for reuse across product families and nodes.
• Experience conducting micro-architectural, RTL, verification, and design reviews to ensure execution quality and mitigate first-silicon risk.
• Strong cross-functional collaboration and communication skills to work with design, product, systems, packaging, and ecosystem partners.

Nice-to-have:

• Experience collaborating across DRAM silicon, ASIC logic, packaging, high-speed interfaces, or system architecture.
• Experience engaging with customers, ecosystem partners, or industry standards organizations (for example, JEDEC).
• Demonstrated technical leadership across multiple projects or product generations.
• Familiarity with system-level trade-offs involving signal integrity, thermals, or cost.

Education Requirements

Bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required. Preferred: Master's or PhD (or equivalent practical experience) in a relevant engineering or computer science discipline.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.