Modelling Lead (SystemC / Virtual-Platform Architect)

Job Title

Modelling Lead — SystemC / Virtual-Platform Architect

Role Summary

Lead development of a pre-silicon virtual platform and architecture/performance models used to validate firmware and guide microarchitectural decisions. This is a founding, critical-path engineering role that enables firmware bring-up, DV scoreboards, and early architectural trade-offs.

Experience Level

Senior — expects 8+ years of relevant experience in architecture/performance modelling or virtual-platform development for complex SoCs.

Responsibilities

Primary responsibilities focus on building executable models and using them to drive architecture and verification decisions.

• Design and implement a SystemC/TLM-2.0 virtual platform: MCU (ISS-backed), peripherals, memory map, UCIe transactor, and host stub that firmware can run on pre-RTL.
• Create architecture and performance models for end-to-end datapath throughput, latency, FIFO/buffer sizing, and configuration exploration.
• Produce golden reference models delivered to DV as scoreboards and verification references.
• Develop behavioral models for analog and control circuits where needed for system-level evaluation.
• Integrate third-party ISS cores (e.g., Arm or RISC-V) and model buses, memory maps, and peripherals within the platform.
• Partner with front-end architects and firmware leads to keep model, RTL, and firmware views consistent.
• Perform architectural trade studies and settle design decisions that are costly to change late.
• Ensure the platform supports running real firmware for pre-silicon bring-up and validation.

Requirements

Must-have technical skills and experience; preferred items listed separately.

Must-have:

• 8+ years in architecture/performance modelling or virtual-platform development for complex SoCs.
• Strong SystemC and TLM-2.0 experience and solid modern C++ skills.
• Proven delivery of a virtual platform/ESL model that real firmware ran on for pre-silicon bring-up.
• Experience integrating a third-party ISS (Arm or RISC-V) into SystemC/TLM platforms and modelling buses, memory maps, and peripherals.
• Good architecture/performance modelling judgment—ability to choose appropriate abstraction vs fidelity.
• Comfortable spanning hardware micro-architecture and embedded software concerns.

Nice-to-have:

• Familiarity with high-speed serial links and die-to-die / chiplet interconnects; link-layer concepts such as FEC and equalization (examples: PCIe, UALink, Ethernet, memory-semantic interconnects like CXL).
• Experience feeding golden models into a UVM/DV verification flow.
• Modelling experience for mixed-signal or optical/SerDes systems, including control-loop / plant modelling.
• Experience with high-throughput datapath modelling.

Education Requirements

Not specified.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.