Modeling Architect

Job Title

Modeling Architect

Role Summary

Hands-on architecture modeler for the T100 optical inference accelerator, responsible for hardware/software co-design and end-to-end performance, power, and functional modeling. Work spans analytical system performance and detailed hardware models, collaborating with architects, compiler/runtime, and RTL teams.

Onsite role based in Austin, TX or Sunnyvale, CA; reports to the Sr. Director of Modeling.

Experience Level

Senior — requires 3+ years of experience in hardware modeling, performance simulation, computer architecture, or equivalent work.

Responsibilities

Primary responsibilities include building and validating performance and functional models and translating workloads to the accelerator programming model.

• Integrate and run inference workloads (dense, MoE, SSM/hybrid, prefill vs decode, KV cache, expert routing, quantized models) and map retrieval, speech, vision, and recommendation workloads to the accelerator.
• Bind Hugging Face and PyTorch workloads to the programming model and execute them on functional models.
• Co-design tiling, scheduling, ISA, SRAM/HBM hierarchy, and multi-chip mappings with hardware teams.
• Develop modeling stack layers: roofline/limiter analyses, Python energy/latency models, C++ functional models (optical GEMM, vector processors, dataflow engines), cycle-approximate performance and power models, and RTL simulation workflows.
• Maintain reproducible tests, configurations, plots, and documentation for all results.
• Use and review outputs from coding agents for multi-file edits; own review of generated C++ and SystemVerilog.
• Present results to architects and cross-functional teams and iterate on models based on feedback.

Requirements

Must-have technical skills and experience for immediate contribution.

• 3+ years in hardware modeling, performance simulation, computer architecture, or similar roles.
• Proficiency in Python or modern C++ (C++17+); comfortable in either a Python-first or C++-first workflow.
• Working knowledge of computer architecture and microarchitecture: pipelines, caches, memory hierarchies, and ISAs.
• Ability to convert papers (LLM, GEMM, accelerator) into workload configs and run them using Hugging Face or PyTorch.
• Strong debugging skills and disciplined documentation of experiments, assumptions, and results.

Education Requirements

BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field is listed as the baseline; MS or PhD in those fields is preferred.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.