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ML/AI Timing and Power Flow Engineer

Altera
October 13, 2026
Full-time
On-site
San Jose, California, United States
$127,400 - $184,400 USD yearly
Physical Design Jobs, Level - Senior

Job Title

ML/AI Timing and Power Flow Engineer

Role Summary

Engineers and improves timing, power, and library characterization flows for ASIC/FPGA implementation and signoff. The role combines deep methodology and flow expertise (STA, power analysis, UPF, library generation) with ML/AI techniques to accelerate flow development, debug, and QoR improvements.

This is a cross-functional position working with physical design, library, CAD, power, and reliability teams to achieve timing and power convergence at block and full-chip levels.

Experience Level

Senior - expects at least 8+ years of relevant industry experience; multiple items list 6+ years for specific technical areas.

Responsibilities

Primary responsibilities include developing, validating, and automating timing and power signoff flows and applying data-driven methods to improve flow efficiency and convergence.

  • Develop, enhance, and maintain timing and power flows across the physical design and signoff lifecycle.
  • Own and drive STA flows: timing setup, analysis, and timing collateral generation.
  • Design and implement power-aware flows, including UPF integration, power intent validation, and power/timing reporting.
  • Lead standard-cell and macro library generation and characterization: timing, power, noise, constraints, and validation for signoff readiness.
  • Integrate characterized libraries into STA and power flows and ensure quality checks for signoff.
  • Build and maintain scalable, automated flow infrastructure using sound software engineering practices.
  • Apply ML/AI techniques to accelerate flow development, automate bottleneck analysis, detect anomalies, and predict QoR trends.
  • Generate, analyze, and review timing, power, and library reports to ensure accuracy and signoff quality.
  • Collaborate with PD, STA, library, power, and methodology teams to improve flows and usability.
  • Debug complex timing, power, library, and flow issues across multiple design stages and configurations.

Requirements

Must-have technical skills and experience; preferred items listed separately.

  • Minimum 8+ years of relevant industry experience overall.
  • 6+ years experience in timing and power flow development and methodology.
  • 6+ years experience with industry-standard STA, power analysis, and library characterization tools.
  • 6+ years of coding and automation experience (Tcl, Python, Perl, or similar) with emphasis on clean, reusable, maintainable flow infrastructure.
  • Deep understanding of timing concepts, STA methodologies, timing constraints, and timing collateral generation.
  • 6+ years experience in power analysis, optimization techniques, and comprehensive power reporting methodologies, including multi-power-domain UPF work.
  • Hands-on experience with library generation and characterization (timing, power, noise models) and integration into STA/power flows.
  • Demonstrated interest or experience applying ML/AI or data-driven techniques to flow automation, debug, QoR prediction, or trend analysis.

Nice-to-have

  • Experience supporting advanced-node, large-scale SoC designs (multi-million instance designs across multiple power domains).
  • Experience with ML/AI frameworks, data analytics platforms, or statistical methods applied to EDA, timing/power analysis, or library characterization.
  • Proven experience translating deep data analysis into measurable methodology and flow improvements and independently driving methodology enhancements to production.
  • Strong cross-functional collaboration and technical communication experience (PD, STA, library, CAD, power).

Education Requirements

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is specified (minimum) in the posting; the role also requires substantial industry experience (8+ years). No explicit mention of Master's, PhD, certifications, or "equivalent experience" language was provided.


About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.

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Date Posted: 2026-10-08