Mixed Signal Verification Architect

Job Title

Mixed Signal Verification Architect

Role Summary

Define scalable verification and validation methodologies for mixed-signal digital power management products used in AI, datacenter, and high-performance computing. Focus on system-level verification that links analog behavior, digital implementation, firmware, tooling, validation data, and silicon correlation.

Align cross-functional teams around measurable evidence and reusable verification patterns to improve confidence in architecture and product decisions.

Experience Level

Senior — approximately 8+ years of relevant experience in mixed-signal verification, semiconductor validation, systems engineering, analog/mixed-signal design, or related product development.

Responsibilities

Main responsibilities include setting verification strategy, defining measurable criteria, and ensuring correlation between models and silicon.

• Define verification strategy for digital power controllers and power-management products.
• Develop system-level verification plans covering sensing paths, ADC/DAC behavior, PWM paths, telemetry, compensation, control-loop behavior, latency, quantization, noise, limits, sequencing, and corner cases.
• Establish correlation methodologies across behavioral models, RTL, analog/mixed-signal simulations, emulation, bench validation, and silicon measurements.
• Define measurable pass/fail criteria, coverage expectations, reference scenarios, and evidence requirements for architecture and product decisions.
• Collaborate with systems, analog/digital design, firmware, design verification, validation, applications, and software/tool teams.
• Support automation of verification results: consistent metrics, plots, waveforms, summaries, and structured outputs for engineering review.
• Identify verification gaps early and reduce ambiguity between system intent, implementation behavior, and validation evidence.
• Document verification methodology, interface assumptions, test intent, correlation expectations, and residual risks for technical and leadership audiences.

Requirements

Must-have technical skills and experience.

• 8+ years in mixed-signal verification, semiconductor validation, systems engineering, analog/mixed-signal design, or design verification.
• Deep understanding of analog and mixed-signal building blocks: ADCs, DACs, amplifiers, references, sensing paths, timing circuits, PWM paths, and power stages.
• Experience defining verification plans, validation methodologies, measurable results, and technical evidence for complex electronic systems.
• Proven ability to work across analog, digital, firmware, validation, applications, and software/tool teams.
• Strong written and verbal communication; able to explain complex cross-domain verification issues clearly.

Nice-to-have:

• Experience with digital multiphase controllers, DC/DC converters, voltage regulators, power-management ICs, or high-current datacenter power applications.
• Familiarity with model-to-silicon correlation, behavioral modeling, real-number modeling, Verilog-AMS, SystemVerilog RNM, MATLAB, Python, SIMPLIS, or similar environments.
• Experience with verification automation, data analysis, test infrastructure, dashboards, databases, or API-driven workflows.
• Knowledge of control loops, stability, latency, quantization, noise, telemetry, and power-system measurement techniques.
• Experience creating reusable verification frameworks that reduce manual test setup and improve quality.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline required.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.