Mixed-Signal Systems and Verification Engineer II

Job Title

Mixed-Signal Systems and Verification Engineer II

Role Summary

Develop and verify analog and mixed-signal behavioral models and integrate them with digital RTL to ensure designs meet specifications.

Collaborate with analog, digital, and systems teams to debug mixed-domain issues, maintain verification infrastructure, and support delivery of production silicon.

Experience Level

Mid-level (Engineer II). The posting indicates 0–2+ years of relevant experience.

Responsibilities

Primary responsibilities include model development, verification, and cross-domain debugging.

• Develop accurate, simulation-efficient real-number models (RNM) and analog/mixed-signal behavioral models in SystemVerilog.
• Verify that behavioral models represent analog schematics and design intent; integrate models with RTL environments.
• Create and run SystemVerilog testbenches, test scenarios, and assertions (including analog assertion-based verification).
• Support verification of AMS blocks such as ADC/DAC, PLL/VCO/A-DPLL, SerDes, LNA, filters, mixers and related IP.
• Debug verification failures across analog, digital, and mixed-signal domains.
• Develop and maintain verification infrastructure: testbenches, environments, automation scripts, and tooling.
• Document modeling assumptions, verification methodology, and results for formal design and verification reviews.
• Collaborate cross-functionally with design, systems, and IP teams to understand constraints and ensure coverage.

Requirements

Must-have technical skills and core qualifications.

• Strong understanding of SystemVerilog and mixed-signal verification concepts.
• Experience or coursework in real-number modeling (RNM): wreal, UDN/UDT/UDR, Verilog-AMS.
• Basic knowledge of analog and mixed-signal blocks (ADCs, DACs, PLLs, SerDes, RF, signal-processing).
• Familiarity with Cadence Virtuoso Schematic Composer and ADE.
• Strong written and verbal communication; able to work collaboratively in a fast-paced environment.

Nice-to-have:

• Experience developing verification infrastructure, testbenches, and automation; familiarity with UVM.
• Scripting for verification and design automation (Python or Perl).
• Low-power architecture experience; FPGA prototyping; hardware acceleration exposure (Palladium/Protium).
• Familiarity with industry standards (PCIe, USB, DDR) and revision control systems (SOS, SVN, GIT).

Education Requirements

Bachelor's degree in Electrical Engineering or a related field required; MSEE or PhD preferred. The posting also references coursework/experience with RNM and Verilog-AMS.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.