Mixed Signal Modelling and Verification Engineer

Job Title

Mixed Signal Modelling and Verification Engineer

Role Summary

Join the mixed-signal verification team to plan and deliver verification for complex mixed-signal IC developments. The role combines hands-on verification, behavioural modelling, testbench development and leadership of verification activities across the development lifecycle.

Work with engineering teams in the Edinburgh or Newbury office to define verification strategy, improve mixed-signal methodology, and support delivery of production-ready ICs.

Experience Level

Mid-level (Level - Mid-Career). Suitable for engineers with several years of mixed-signal verification or design experience and prior delivery of complex mixed-signal ICs (typical range: 3–7 years).

Responsibilities

Accountable for planning, executing and improving mixed-signal verification for complex ICs. Key responsibilities include:

• Lead mixed-signal verification activities: resource planning, task assignment, progress reporting and delivery.
• Define IC verification strategy, select simulation techniques and verification environments for complex mixed-signal systems.
• Develop reliable, reusable mixed-signal testbenches aligned with industry-standard verification practices.
• Create behavioural models using advanced techniques (real number modelling, user-defined types, Verilog-AMS/VerilogA).
• Provide tool and methodology support to other engineers and improve team verification practices.
• Participate hands-on in testbench development, netlisting and simulation activities.
• Mentor and support junior engineers and collaborate with other disciplines to improve development efficiency.

Requirements

Must-have technical skills and experience, plus preferred skills where noted.

• Proven track record delivering first-time-success for complex mixed-signal ICs.
• Experience with mixed-signal simulation tools and techniques, including Spectre, AMS and digital simulation.
• Strong knowledge of SystemVerilog and practical verification experience.
• Experience with both analog and digital design and the ability to interpret simulation results and resolve issues.
• Experience modelling analog subsystems using SystemVerilog and VerilogA/AMS.
• Highly developed communication skills and problem-solving mindset.
• Preferred: scripting with Python, sh/csh, TCL, Make; object-oriented programming and OOP design patterns.
• Preferred: knowledge of SVA (SystemVerilog Assertions), metric-driven verification, directed and constrained-random techniques, functional/code coverage analysis, power-aware verification (CPF/UPF), and UVM-based testbenches.

Education Requirements

BEng / BSc / MEng / MSc or equivalent in Electronics, Computer Science or a related technical discipline, or equivalent practical experience.

About the Company

Company: Cirrus Logic

Headquarters: Austin, TX, United States

Designer and manufacturer of high-precision analog and mixed-signal integrated circuits, specializing in audio and voice processing solutions for consumer electronics and mobile devices, including audio codecs, converters, and SoCs.