Mixed Signal Logic Design Engineer

Job Title

Mixed Signal Logic Design Engineer

Role Summary

Member of the Memory PHY Group (MPG) within the Central Engineering Group. Responsible for logic design of high-speed, low-power DDRPHY IPs, covering architecture, RTL implementation, front-end quality checks, and delivery to validation and SoC teams.

The role emphasizes automation of front-end flows, improving turnaround and robustness, and cross-functional collaboration across validation, backend and system teams.

Experience Level

Senior — 10+ years of relevant industry experience (Experienced Hire).

Responsibilities

Key responsibilities for the logic design engineer include:

• Define architecture and microarchitecture of mixed-signal IP logic blocks.
• Implement and maintain RTL in SystemVerilog/Verilog.
• Set up and improve automation flows for IP logic design and front-end tooling.
• Ensure RTL quality using front-end tools (Lint, CDC, RDC, voltage-domain crossings, synthesis QA).
• Create front-end packages and deliverables that meet SoC collateral requirements.
• Drive timing closure, coverage closure and timing convergence efforts.
• Optimize IP area and power; propose architecture-level power/area trade-offs.
• Collaborate with validation, backend, and SoC teams; make critical technical decisions.

Requirements

Must-have technical skills and experience, followed by preferred (nice-to-have) items.

• Must-have: 10+ years of relevant industry experience working on digital/mixed-signal IP.
• Must-have: Proficiency in RTL design and coding using SystemVerilog and Verilog.
• Must-have: Expertise in mixed-signal fundamentals, low-power design (UPF, clock gating), clock domain crossing, and power-performance trade-offs.
• Must-have: Experience with hardware simulation and debug tools (e.g., VCS, Verdi) and front-end QA tools (Lint, CDC, RDC, synthesis checks).
• Must-have: Familiarity with IP environments and configuration/version management.
• Nice-to-have: DDR/DFI/LPDDR protocol knowledge; experience debugging complex logic and speed paths.
• Nice-to-have: Exposure to formal property verification, Git version control, pre-silicon and post-silicon validation.
• Nice-to-have: Experience with AI-assisted development tools (e.g., VSCode, GitHub Copilot) and mentoring junior engineers.

Education Requirements

The posting specifies a BS or MS degree and a requirement of 10+ years of relevant industry experience. No specific fields of study or certifications are listed in the source.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.