Mixed Signal Logic Design Engineer

Job Title

Mixed Signal Logic Design Engineer

Role Summary

Design and deliver RTL for high-speed mixed-signal IPs (DDRPHY) with emphasis on low-power, area, and timing optimization. Work across architecture, front-end design, verification, and automation to produce IP deliverables for SoC integration.

Position sits in the Memory PHY Group (MPG) within the Central Engineering Group (CEG) and requires collaboration with verification, backend, validation, and SoC teams to meet IP milestones and quality targets.

Experience Level

Mid-level — requires 3+ years of relevant industry experience.

Responsibilities

Primary responsibilities include ownership of logic design and delivery, improving design robustness and turnaround, and enabling automation and methodology improvements.

• Define architecture and microarchitecture features for mixed-signal blocks.
• Implement RTL in SystemVerilog/Verilog and produce FE packages for IP milestones.
• Set up and maintain automation flows for logic design and delivery.
• Ensure RTL quality using front-end tools (Lint, CDC, RDC, voltage-domain checks, synthesis QA).
• Drive area, power, and timing optimizations for IPs and contribute to trade-off decisions.
• Automate front-end tools, flows, and handoff processes to validation, backend, and SoC teams.
• Collaborate with cross-functional teams and make critical technical decisions during design and delivery.

Requirements

Must-have technical skills and experience.

• Proficiency in RTL design and coding using SystemVerilog and Verilog.
• Expertise in mixed-signal fundamentals and low-power techniques (UPF, clock gating).
• Deep understanding of digital and analog interaction, clock-domain crossings, and power-performance trade-offs.
• Experience with hardware simulation and debug tools (e.g., VCS, Verdi).
• Familiarity with IP environments and configuration management.
• Experience with front-end design tools for Lint, CDC, RDC, voltage-domain crossing checks, synthesis, and low-power verification.
• Strong written and verbal communication and ability to work in a fast-moving, cross-functional team.

Nice-to-have:

• DDR/DFI/LPDDR protocol knowledge and DDR design experience.
• Experience with formal property verification, Git version control, and pre-/post-silicon validation.
• Exposure to AI-assisted development tools (e.g., GitHub Copilot) and VS Code workflows.
• Mentoring or leadership experience within small engineering teams.

Education Requirements

Requires a BS or MS degree (Bachelor's or Master's). The posting specifies a BS or MS degree and notes 3+ years of industry experience; no specific field of study or certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.