Mixed-Signal Integrated Circuit Design Engineer – Power Electronics

Job Title

Mixed-Signal Integrated Circuit Design Engineer – Power Electronics

Role Summary

Design and validate robust analog and mixed-signal integrated circuits operating across low- and high-voltage domains (up to ~200 V) in BCD and high-voltage CMOS technologies. The role partners with electrochemistry, microfluidics, layout, and test teams to deliver silicon for automated biological synthesis systems requiring precise high-voltage control and switching.

Experience Level

Mid-level — minimum of 5+ years of relevant integrated circuit design experience.

Responsibilities

Contribute to architecture, detailed design, and silicon validation of high-voltage analog/mixed-signal circuits.

• Define system and circuit requirements with a multidisciplinary team.
• Architect and design circuits spanning LV and HV domains, including technology-node selection.
• Design high-voltage drivers, level shifters, isolation structures, bias/reference and sensing circuits, and protection/reliability features.
• Perform schematic design, simulation, and post-layout verification.
• Collaborate with layout to implement HV-safe structures and ensure LVS/DRC/PEX compliance.
• Evaluate device stress, SOA, lifetime reliability and implement risk mitigation.
• Lead silicon bring-up, characterization, debugging, and failure analysis.

Requirements

Must-have skills and experience required to perform the role.

• At least 5 years of IC design experience with direct, production-focused work in high-voltage technologies (BCD, HV CMOS, SOI, or power IC processes).
• Transistor-level analog design experience: current/voltage biasing, bandgap references, amplifiers, LDOs, DAC/ADC blocks, and level shifters.
• Design and analysis for reliability, device stress, and SOA in high-voltage circuits.
• Experience designing efficient high-voltage driver circuits for capacitive or electrochemical loads (kHz–MHz range).
• Hands-on use of Cadence Virtuoso, Spectre or equivalent for pre- and post-layout simulation, noise/mismatch analysis, and Monte Carlo.
• Layout collaboration and practical knowledge of LVS, DRC, and post-layout extraction (PEX).
• Silicon bring-up, characterization, debugging, and participation in failure analysis.
• Understanding of ESD protection and latch-up mechanisms and mitigation strategies.
• Strong communication and teamwork skills; ability to work in a fast-paced startup environment.

Nice-to-have:

• Verilog-A modeling and analog-mixed-signal (AMS) simulation experience.
• Prior experience with very-high-voltage designs (~100–200 V) or power IC design.

Education Requirements

PhD in Electrical Engineering or a related discipline, or an MS/BS in a related field with ~5 years of relevant experience as stated (PhD preferred). No certifications specified.

About the Company

Company: Avery Bio

Headquarters: San Diego, CA, USA

Developer of an automated genetic engineering platform that integrates semiconductor-based chips to scale the synthesis, assembly, and testing of genetic components in cell-free and cellular environments. Targets applications across drug discovery, precision medicine, advanced materials, and sustainable agriculture.