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Mixed-Signal Design Verification Engineer

Allegro MicroSystems
September 21, 2026
Full-time
On-site
Manchester, New Hampshire, United States
Verification Jobs, Level - Entry or Early Career

Job Title

Mixed-Signal Design Verification Engineer

Role Summary

Develop and execute top-level mixed-signal verification testbenches for automotive and industrial integrated circuits. Work with senior technical leads and partner with Analog, Digital, and Systems Engineering to verify chip-level analog-digital interactions and support first-pass silicon success.

Experience Level

Entry-level (1–3 years of relevant industry or internship experience).

Responsibilities

Primary responsibilities include verification planning, simulation, and cross-team coordination to validate system behavior.

  • Develop and run top-level AMS simulations (Cadence AMS Designer, Virtuoso) to validate interactions between analog front-ends and digital logic.
  • Create and maintain behavioral models and testbenches in Verilog, SystemVerilog, and Verilog-AMS/Real-Number Modeling.
  • Verify power-up/power-down sequences, brown-out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners.
  • Validate register maps, EEPROM/configuration loads, read/write protocols, and trim/test modes against specifications.
  • Log and track verification issues in GitLab and drive bugs to closure to support tapeout readiness.
  • Review coverage metrics in requirements tools (e.g., Jama Connect) and support testcase closure with cross-functional teams.

Requirements

Must-have technical skills and practical experience; a few nice-to-have items are listed below.

  • Must-have: 1–3 years of experience in mixed-signal design verification or IC design.
  • Must-have: Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).
  • Must-have: Working knowledge of Verilog and SystemVerilog.
  • Must-have: Solid understanding of fundamental analog circuits (amplifiers, bandgaps, LDOs, ADCs) and basic digital logic.
  • Nice-to-have: Introductory experience with Verilog-A/AMS and Real-Number Modeling (RNM/wreal).
  • Nice-to-have: Basic Linux and scripting skills (Python, Bash, or Skill).
  • Nice-to-have: Experience with issue-tracking (GitLab) and requirements management (Jama Connect).
  • Strong written and verbal communication and a collaborative mindset.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline (specified in the posting). The posting does not state an explicit alternative of "or equivalent experience."


About the Company

Company: Allegro MicroSystems

Headquarters: Manchester, New Hampshire, USA

Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.

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Date Posted: 2026-09-21