Mixed-Signal Design Verification Engineer — Custom

Job Title

Mixed-Signal Design Verification Engineer — Custom

Role Summary

Member of the Top-Level Design Verification (TLDV) team within the ACS product line responsible for pre-silicon verification of mixed-signal ASSP ICs. The team builds automated AMS and DMS testbenches to verify functionality, electrical parameters, performance and reliability of high-volume custom chips.

This role focuses on verifying high-speed wireline communications and clock/data paths, improving verification tools and methodologies, and collaborating with design and systems teams to close issues before tapeout.

Experience Level

Senior — minimum 8+ years of design verification experience; includes at least 4+ years verifying high-speed clock/data paths (e.g. USB, SerDes, PLL, DLL).

Responsibilities

Primary duties include pre-silicon verification, creating scalable testbenches and models, and collaborating with cross-functional teams.

• Develop and execute pre-silicon AMS/DMS/TLDV testbenches and automation to verify DUT behavior before tapeout.
• Verify high-speed clock and data paths: clock/data recovery, timing, serialization/deserialization, PLLs, DLLs, and wireline protocols (USB, eUSB, SerDes).
• Validate designs against datasheets, VVCM, system-level use cases, DFT features, and customer/bench/ATE expectations.
• Work with designers and systems engineers to define design-for-verification architecture, triage bugs, and clarify specifications.
• Recreate system-level use cases in simulation and communicate results with customers when needed.
• Create and maintain behavioral models of analog circuits (real-number, wreal/Verilog-AMS, or simple schematic models).

Requirements

Must-have:

• Extensive design verification experience with mixed-signal and digital flows (AMS / DMS / TLDV / DDV).
• Strong understanding of analog and digital design at schematic and RTL levels, including PVT effects, layout parasitics, timing, FSMs, synchronization, power and clock domains.
• Experience verifying timing with Gates+SDF and timing across analog/digital boundaries.
• Proficiency with verification languages and tools such as Verilog, SystemVerilog, Verilog-AMS, Cadence Virtuoso/Spectre, Simvision, and scripting for automation.
• Experience building scalable automation, data collection and analysis tools for verification and simulation.
• Strong debugging, analytical, communication and cross-team leadership skills; customer-facing experience.

Nice-to-have:

• Experience verifying USB (USB2.0, eUSB), re-timers/re-drivers, or SerDes interfaces.
• Experience modeling analog blocks as real-number models in SystemVerilog.
• Familiarity with Verification IPs (VIPs) for USB, eUSB, PLLs, or SerDes.

Education Requirements

Bachelor's degree (Job lists Degree Level: Bachelor's Degree). Field of study not specified.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.