Mixed Signal Design Verification Engineer

Job Title

Mixed Signal Design Verification Engineer

Role Summary

Perform functional verification of mixed-signal IPs (for example PCIe, UCIE, USB4/Type-C PHYs) by developing verification plans, testbenches, simulation models, and coverage-driven tests. Work with digital and analog architects, RTL developers, and physical design teams to find and resolve design issues and to improve verification infrastructure and methodologies.

Experience Level

Mid-level. Typical experience expectation: multi-year industry experience (see Education Requirements for specific guidance).

Responsibilities

Primary responsibilities focus on validating mixed-signal designs pre-silicon, improving verification quality, and collaborating across teams.

• Perform functional verification of mixed-signal logic and analog behavioral models to verify compliance with specifications.
• Develop IP verification plans, testbenches, and environments to achieve coverage goals.
• Define and run simulation models to verify performance, power, and timing; analyze results and report issues.
• Execute constraint-random and directed tests; debug failures and perform root-cause analysis.
• Collaborate with architects, RTL designers, and physical design teams to refine architecture and microarchitecture.
• Lead technical reviews of test plans and validation evidence; document findings and corrective actions.
• Maintain and improve verification methodologies, infrastructure, and tools.

Requirements

Must-have technical skills and tools for day-to-day verification work; preferred items follow.

• Must-have: Strong experience with SystemVerilog, UVM, and Verilog for IP verification.
• Must-have: Hands-on experience with simulation/verification EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Must-have: Scripting for automation: Python, Perl, or Tcl.
• Must-have: Experience with constraint-random test generation, coverage-driven verification, and complex debug/root-cause analysis in mixed-signal environments.
• Must-have: Familiarity with protocols and interfaces including JTAG, IJTAG, CRI, APB and multi-clock-domain mixed-signal designs.
• Nice-to-have: Experience with low-power techniques (UPF, clock gating) and formal property verification tools.
• Nice-to-have: Experience with version control systems such as Git or Perforce and prior work on PCIe/UCIE/USB4/Type-C PHY verification.

Education Requirements

Bachelor's or Master’s degree in Electrical, Electronics, Computer Engineering, or a related field is stated as the baseline. Experience guidance from the posting: 3+ years industry experience with a Bachelor's degree, 2+ years with a Master's degree, or 0 years with a PhD. Equivalent practical experience is acceptable where indicated.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.