Mixed-Signal Design Verification Engineer
Oho GroupJob Title
Mixed-Signal Design Verification Engineer
Role Summary
Contract role to develop and execute mixed-signal (AMS/DMS) verification and testbenches for wireless RF and high-speed PHY designs. Works closely with analog/RF designers and silicon validation teams to support bring-up and commercialization.
Duration: 6+ months. Onsite in San Jose, CA. Pay range: $125/hr - $1555/hr (W2).
Experience Level
Mid-level — requires approximately 3+ years of relevant experience in mixed-signal verification and VLSI simulation flows.
Responsibilities
Primary responsibilities include building verification infrastructure, debugging, and supporting silicon validation.
- Create and maintain AMS/DMS testbenches for wireless RF and high-speed PHYs.
- Integrate analog circuit models with digital verification environments and collaborate with RF/analog design engineers.
- Develop and run mixed-mode and analog simulations; perform waveform analysis and debug.
- Implement digital verification components using Verilog/SystemVerilog and UVM where needed.
- Support silicon bring-up, root-cause analysis, and commercialization activities.
- Collaborate with cross-functional teams to resolve design and verification issues.
Requirements
Must-have technical skills and experience.
- Deep understanding of digital VLSI simulation flows.
- Deep understanding of mixed-mode and analog simulation flows.
- Proficiency with Verilog/SystemVerilog and RNM modeling.
- Experience with digital verification methodologies (UVM) and waveform debug.
- Strong communication, teamwork, and interpersonal skills.
Nice-to-have:
- Experience with wireless RF transceivers and SerDes PHY technology.
Education Requirements
Bachelor's degree (BS or BE) required. No specific field of study was specified in the posting.
About the Company
Company: Oho Group
Recruitment firm/agency advertising engineering and technical roles. In this posting they represent an early-stage AI accelerator startup in the San Francisco Bay Area seeking a Staff RTL Design Engineer experienced in SoC/ASIC RTL, interconnects, and memory subsystems.
