Mixed Signal Design Engineer
AeonsemiJob Title
Mixed Signal Design Engineer
Role Summary
Design high-performance RF/analog/mixed-signal circuits for high-speed wireline transceiver products using advanced CMOS technologies. Work within a cross-functional design team focused on timing and networking solutions for data communications.
Deliver designs from block-level architecture through schematic, simulation, layout coordination, and lab characterization to support product development and production test flows.
Experience Level
Entry-level / Early-career — minimum 2 years of relevant industry experience is expected.
Responsibilities
Primary responsibilities include circuit design, validation, and hands-on verification:
- Define block-level architecture for RF/analog/mixed-signal functions.
- Create schematics, run circuit simulations, develop behavioral models, and produce validation plans.
- Supervise layout engineers and perform hands-on layout of critical paths when required.
- Perform lab characterization and correlate silicon measurements to simulations.
- Collaborate with cross-functional teams on simulation, modeling, and production test flows.
Requirements
Must-have technical skills and experience:
- Solid understanding of analog fundamentals: biasing circuits, clock generation, and/or data converters.
- Proficient with the Cadence design environment for schematic entry and simulation.
- Effective verbal and written communication skills for team collaboration and documentation.
Nice-to-have:
- Proficiency in Python or a similar programming language.
- Basic signal processing knowledge.
- Interest in spanning mixed-signal design, simulation/modeling, and production test/debug flows.
Education Requirements
MS or Ph.D. in Electrical Engineering is required; the posting specifies a minimum of 2 years of relevant experience. Fields referenced: electrical engineering and related technical areas.
About the Company
Company: Aeonsemi
Headquarters: Mundelein, IL, USA
Pre-IPO semiconductor design company developing high-speed data communication and timing solutions for Physical AI. Designs synchronous Ethernet networking and timing products for secure connectivity, precise synchronization, and efficient power delivery across AI edge nodes, autonomous systems, and hyperscale data centers. Focused on mixed-signal and RF CMOS transceiver design.
