Mid-level Physical Design Engineer, CPU

Job Title

Mid-level Physical Design Engineer, CPU

Role Summary

Work on block-level physical design for CPU cores, contributing across the RTL-to-GDS implementation flow to deliver high-performance, power-efficient silicon on advanced process nodes.

Collaborate with RTL design, verification, clocking, and full-chip teams to achieve timing, power, and area targets and improve design flows and automation.

Experience Level

Mid-level. Typical experience: approximately 3–7 years of relevant physical design or IC implementation work.

Responsibilities

The primary responsibilities focus on physical implementation, verification, and automation for CPU core blocks and subsystems.

• Execute synthesis, floorplanning, place-and-route (PnR), and design closure for CPU blocks.
• Perform static timing analysis (STA), power analysis, and physical verification; identify and debug timing, power, and DRC/LVS issues.
• Contribute to meeting timing, power, and area (PPA) targets for assigned blocks.
• Develop and maintain automation scripts (TCL and at least one other scripting language such as Python or Perl).
• Collaborate with RTL, verification, clocking, and full-chip integration teams to ensure correct integration and handoff.
• Support improvements to design flows, methodologies, and best practices; document technical work and share knowledge within the team.

Requirements

Must-have technical skills and practical experience required for initial consideration. Preferred items are listed as nice-to-have.

• Experience with IC design tool flows: logic synthesis, place-and-route, static timing analysis and design closure (Synopsys or Cadence tool experience expected).
• Experience with PV convergence, static timing and power analysis, and debugging timing/power closure issues.
• Experience with physical design verification: formal equivalence, timing and electrical rule checks, DRC/LVS, noise and electromigration checks.
• Scripting experience in interpreted languages; TCL is required plus at least one other (e.g., Python, Perl, Ruby) for automation.
• Proven experience synthesizing digital logic blocks and integrating them into a large SoC or IP environment.
• Behavioral/soft skills: strong analytical problem-solving, ownership and accountability, effective cross-functional communication, adaptability and continuous learning.

Nice-to-have:

• Exposure to CPU micro-architecture.
• Knowledge of floor-planning, routing techniques, and clock-distribution best practices for physical design.
• Experience with Synopsys Fusion Compiler/ICC2/PrimeTime or Cadence Genus/Innovus tool suites.
• Familiarity with RTL-to-GDS methodologies and formal equivalence flows.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical Engineering, or a related technical field with 5+ years of relevant experience; or Master's degree in a related field with 3+ years of relevant experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.